View M58LR128KC765_4771927.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

M58LR128KC, M58LR128KD M58LR256KC, M58LR256KD
128 or 256 Mbit (x16, mux I/O, multiple bank, multilevel interface, burst) 1.8 V supply Flash memories
Target Specification
Features
Supply voltage - VDD = 1.7 V to 2.0 V for program, erase and read - VDDQ = 1.7 V to 2.0 V for I/O buffers - VPP = 9 V for fast program Multiplexed address/data Synchronous/asynchronous read - Synchronous burst read mode: 66 MHz, 86 MHz - Random access: 70 ns Synchronous burst read suspend Programming time - 2.5 s typical word program time using Buffer Enhanced Factory Program command Memory organization - Multiple bank memory array: 8 Mbit banks for the M58LR128KC/D 16 Mbit banks for the M58LR256KC/D - Parameter blocks (top or bottom location) Dual operations - Program/erase in one bank while read in others - No delay between read and write operations Common Flash interface (CFI) 100 000 program/erase cycles per block

Wafer

Block locking - All blocks locked at power-up - Any combination of blocks can be locked with zero latency - WP for block lock-down - Absolute write protection with VPP = VSS Security - 64 bit unique device number - 2112 bit user programmable OTP Cells Electronic signature - Manufacturer code: 20h - Top device codes: M58LR128KC: 882Eh M58LR256KC: 881Ch - Bottom device codes M58LR128KD: 882Fh M58LR256KD: 881Dh

The M58LRxxxKC/D memories are only available as part of a multichip package.
March 2008
Rev 3
1/108
www.numonyx.com 1
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
Contents
M58LRxxxKC, M58LRxxxKD
Contents
1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 2.15 Address inputs (ADQ0-ADQ15 and A16-Amax) . . . . . . . . . . . . . . . . . . . . 13 Data input/output (ADQ0-ADQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Reset (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Clock (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Wait (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 VDD supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 VDDQ supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 VPP program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 VSSQ ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1 3.2 3.3 3.4 3.5 3.6 Bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Address Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4
Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1 4.2 4.3 4.4 Read Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Read Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Read Electronic Signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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Contents
4.5 4.6 4.7 4.8 4.9 4.10
Clear Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Blank Check command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Buffer Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Buffer Enhanced Factory Program command . . . . . . . . . . . . . . . . . . . . . 23
4.10.1 4.10.2 4.10.3 Setup phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Program and verify phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Exit phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.11 4.12 4.13 4.14 4.15 4.16 4.17
Program/Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Program/Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Protection Register Program command . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Set Configuration Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Block Lock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Block Unlock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Block Lock-Down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 Program/Erase Controller status bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . 33 Erase suspend status bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Erase/blank check status bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Program status bit (SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 VPP status bit (SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Program suspend status bit (SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Block protection status bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Bank write/multiple word program status bit (SR0) . . . . . . . . . . . . . . . . . 35
6
Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.1 6.2 6.3 6.4 6.5 6.6 Read select bit (CR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 X latency bits (CR13-CR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Wait polarity bit (CR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Data output configuration bit (CR9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Wait configuration bit (CR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Burst type bit (CR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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Contents
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6.7 6.8 6.9
Valid clock edge bit (CR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Wrap burst bit (CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Burst length bits (CR2-CR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7
Read modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.1 7.2 7.3 Asynchronous read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Synchronous burst read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.2.1 Synchronous burst read suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Single synchronous read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8 9
Dual operations and multiple bank architecture . . . . . . . . . . . . . . . . . 47 Block locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9.1 9.2 9.3 9.4 9.5 Reading a block's lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Locked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Unlocked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Lock-down state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Locking operations during erase suspend . . . . . . . . . . . . . . . . . . . . . . . . 50
10 11 12 13
Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 52 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Part ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Appendix A Block address tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Appendix B Common Flash interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Appendix C Flowcharts and pseudocodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Appendix D Command interface state tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
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M58LRxxxKC, M58LRxxxKD
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 M58LR128KC/D bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 M58LR256KC/D bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Standard commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Factory commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Electronic signature codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Protection Register locks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 X latency settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Burst type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Dual operations allowed in other banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Dual operations allowed in same bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Dual operation limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Program/erase times and endurance cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 DC characteristics - currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 DC characteristics - voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Asynchronous read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Synchronous read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Write AC characteristics, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Write AC characteristics, chip enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Reset and power-up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 M58LR128KC - parameter bank block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 M58LR128KC - main bank base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 M58LR128KC - block addresses in main banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 M58LR256KC - parameter bank block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 M58LR256KC - main bank base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 M58LR256KC - block addresses in main banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 M58LR128KD - parameter bank block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 M58LR128KD - main bank base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 M58LR128KD - block addresses in main banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 M58LR256KD - parameter bank block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 M58LR256KD - main bank base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 M58LR256KD - block addresses in main banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 CFI query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 CFI query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Protection Register information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Burst read information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
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List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56.
M58LRxxxKC, M58LRxxxKD
Bank and erase block region information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Bank and erase block region 1 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Bank and erase block region 2 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Command interface states - modify table, next state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Command interface states - modify table, next output state . . . . . . . . . . . . . . . . . . . . . . 101 Command interface states - lock table, next state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Command interface states - lock table, next output state . . . . . . . . . . . . . . . . . . . . . . . . 105 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
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M58LRxxxKC, M58LRxxxKD
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 M58LR128KC/D memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 M58LR256KC/D memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Protection Register memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 X latency and data output configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Wait configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Asynchronous random access read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Synchronous burst read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Single synchronous read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Synchronous burst read suspend AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Clock input AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Write AC waveforms, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Write AC waveforms, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Reset and power-up AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Blank check flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Buffer program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Program suspend and resume flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . 92 Block erase flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Erase suspend and resume flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Locking operations flowchart and pseudocode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Protection Register program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Buffer enhanced factory program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . 97
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Description
M58LRxxxKC, M58LRxxxKD
1
Description
The M58LR128KC/D and M58LR256KC/D are 128 Mbit (8 Mbit x16) and 256 Mbit (16 Mbit x16) non-volatile Flash memories, respectively. They may be erased electrically at block level and programmed in-system on a word-by-word basis using a 1.7 V to 2.0 V VDD supply for the circuitry and a 1.7 V to 2.0 V VDDQ supply for the input/output pins. An optional 9 V VPP power supply is provided to speed up factory programming. In the rest of the document they are collectively referred to as the M58LRxxxKC/D unless otherwise specified. The first sixteen address lines are multiplexed with the data input/output signals on the multiplexed address/data bus ADQ0-ADQ15. The remaining address lines A16-Amax are the most significant bit addresses. The devices feature an asymmetrical block architecture:
The M58LR128KC/D has an array of 131 blocks, and are divided into 8 Mbit banks. There are 15 banks each containing 8 main blocks of 64 KWords, and one parameter bank containing 4 parameter blocks of 16 KWords and 7 main blocks of 64 KWords. The M58LR256KC/D has an array of 259 blocks, and is divided into 16 Mbit banks. There are 15 banks each containing 16 main blocks of 64 KWords, and one parameter bank containing 4 parameter blocks of 16 KWords and 15 main blocks of 64 KWords.
The multiple bank architecture allows dual operations; while programming or erasing in one bank, read operations are possible in other banks. Only one bank at a time is allowed to be in program or erase mode. It is possible to perform burst reads that cross bank boundaries. The bank architectures are summarized in Table 2 and Table 3 and the memory maps are shown in Figure 2 and Figure 3. The parameter blocks are located at the top of the memory address space for the M58LR128KC and M58LR256KC, and at the bottom for the M58LR128KD and M58LR256KD. Each block can be erased separately. Erase can be suspended to perform a program or read operation in any other block, and then resumed. Program can be suspended to read data at any memory location except for the one being programmed, and then resumed. Each block can be programmed and erased over 100 000 cycles using the supply voltage VDD. There is a Buffer Enhanced Factory Programming command available to speed up programming. Program and erase commands are written to the command interface of the memory. An internal Program/Erase Controller manages the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified in the Status Register. The command set required to control the memory is consistent with JEDEC standards. The device supports synchronous burst read and asynchronous read from all blocks of the memory array; at power-up the device is configured for asynchronous read. In synchronous burst read mode, data is output on each clock cycle at frequencies of up to 86 MHz. The synchronous burst read operation can be suspended and resumed. The device features an automatic standby mode. When the bus is inactive during asynchronous read operations, the device automatically switches to the automatic standby mode. In this condition the power consumption is reduced to the standby value and the outputs are still driven.
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M58LRxxxKC, M58LRxxxKD
Description
The M58LRxxxKC/D features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. All blocks have three levels of protection. They can be locked and locked-down individually preventing any accidental programming or erasure. There is an additional hardware protection against program and erase. When VPP VPPLK all blocks are protected against program or erase. All blocks are locked at power-up. The device includes 17 Protection Registers and 2 Protection Register locks, one for the first Protection Register and the other for the 16 One-Time-Programmable (OTP) Protection Registers of 128 bits each. The first Protection Register is divided into two segments: a 64 bit segment containing a unique device number written by Numonyx, and a 64 bit segment that is OTP by the user. The user programmable segment can be permanently protected. Figure 4, shows the Protection Register memory map. The devices are supplied with all the bits erased (set to '1') Note: The M58LRxxxKC/D is only available as part of a multichip package.
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Description Figure 1. Logic diagram
VDD VDDQ VPP 16 A16-Amax(1) W E G RP WP L K M58LR128KC M58LR128KD M58LR256KC M58LR256KD
M58LRxxxKC, M58LRxxxKD
ADQ0-ADQ15
WAIT
VSS
VSSQ
AI13453c
1. Amax is equal to A22 in the M58LR128KC/D and, to A23 in the M58LR256KC/D.
Table 1.
A16-Amax(1)
Signal names
Name Address inputs Data input/outputs or address inputs, command inputs Chip Enable Output Enable Write Enable Reset Write Protect Clock Latch Enable Wait Supply voltage Supply voltage for input/output buffers Optional supply voltage for fast program and erase Ground Ground input/output supply Function
ADQ0-ADQ15 E G W RP WP K L WAIT VDD VDDQ VPP VSS VSSQ
1. Amax is equal to A22 in the M58LR128KC/D and, to A23 in the M58LR256KC/D.
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M58LRxxxKC, M58LRxxxKD Table 2. M58LR128KC/D bank architecture
Bank size 8 Mbits 8 Mbits 8 Mbits 8 Mbits ---Parameter blocks 4 blocks of 16 KWords ----
Description
Number Parameter bank Bank 1 Bank 2 Bank 3 ----
Main blocks 7 blocks of 64 KWords 8 blocks of 64 KWords 8 blocks of 64 KWords 8 blocks of 64 KWords ---8 blocks of 64 KWords 8 blocks of 64 KWords
Bank 14 Bank 15
8 Mbits 8 Mbits
-
Figure 2.
M58LR128KC/D memory map
M58LR128KC - Top Boot Block Address lines A22-A16 and ADQ15-ADQ0 000000h 00FFFFh Bank 15 070000h 07FFFFh 64 KWord 64 KWord 8 Main Blocks Parameter Bank
M58LR128KD - Bottom Boot Block Address lines A22-A16 and ADQ15-ADQ0 000000h 003FFFh 00C000h 00FFFFh 010000h 01FFFFh 070000h 07FFFFh 080000h 08FFFFh Bank 1 0F0000h 0FFFFFh 100000h 10FFFFh Bank 2 170000h 17FFFFh 180000h 18FFFFh Bank 3 1F0000h 1FFFFFh 64 KWord 64 KWord 64 KWord 8 Main Blocks 64 KWord 64 KWord 8 Main Blocks 16 KWord 4 Parameter Blocks 16 KWord 64 KWord 7 Main Blocks 64 KWord 64 KWord 8 Main Blocks
600000h 60FFFFh Bank 3 670000h 67FFFFh 680000h 68FFFFh Bank 2 6F0000h 6FFFFFh 700000h 70FFFFh Bank 1 770000h 77FFFFh 780000h 78FFFFh 7E0000h 7EFFFFh 7F0000h 7F3FFFh 7FC000h 7FFFFFh
64 KWord 8 Main Blocks 64 KWord 64 KWord 8 Main Blocks 64 KWord 64 KWord 8 Main Blocks 64 KWord 64 KWord 7 Main Blocks 64 KWord 16 KWord 4 Parameter Blocks Bank 15 16 KWord
Parameter Bank
780000h 78FFFFh 7F0000h 7FFFFFh
64 KWord 8 Main Blocks 64 KWord
AI13454b
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Description Table 3. M58LR256KC/D bank architecture
Bank size 16 Mbits 16 Mbits 16 Mbits 16 Mbits ---Parameter blocks 4 blocks of 16 KWords ----
M58LRxxxKC, M58LRxxxKD
Number Parameter bank Bank 1 Bank 2 Bank 3 ----
Main blocks 15 blocks of 64 KWords 16 blocks of 64 KWords 16 blocks of 64 KWords 16 blocks of 64 KWords ---16 blocks of 64 KWords 16 blocks of 64 KWords
Bank 14 Bank 15
16 Mbits 16 Mbits
-
Figure 3.
M58LR256KC/D memory map
M58LR256KC - Top Boot Block Address lines A23-A16 and ADQ15-ADQ0 000000h 00FFFFh 64 KWord 16 Main Blocks 64 KWord Parameter Bank M58LR256KD- Bottom Boot Block Address lines A23-A16 and ADQ15-ADQ0 000000h 003FFFh 00C000h 00FFFFh 010000h 01FFFFh 0F0000h 0FFFFFh 100000h 10FFFFh Bank 1 1F0000h 1FFFFFh 200000h 20FFFFh Bank 2 2F0000h 2FFFFFh 300000h 30FFFFh Bank 3 3F0000h 3FFFFFh 15 Main Blocks 64 KWord 16 KWord 4 Parameter Blocks 16 KWord Bank 15 FF0000h FFFFFFh 64 KWord
AI13786b
16 KWord 4 Parameter Blocks 16 KWord 64 KWord 15 Main Blocks 64 KWord 64 KWord 16 Main Blocks 64 KWord 64 KWord 16 Main Blocks 64 KWord 64 KWord 16 Main Blocks 64 KWord
Bank 15 0F0000h 0FFFFFh
C00000h C0FFFFh Bank 3 CF0000h CFFFFFh D00000h D0FFFFh Bank 2 DF0000h DFFFFFh E00000h E0FFFFh Bank 1 EF0000h EFFFFFh F00000h F0FFFFh FE0000h FEFFFFh FF0000h FF3FFFh FFC000h FFFFFFh
64 KWord 16 Main Blocks 64 KWord 64 KWord 16 Main Blocks 64 KWord 64 KWord 16 Main Blocks 64 KWord 64 KWord
Parameter Bank
F00000h F0FFFFh
64 KWord 16 Main Blocks
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M58LRxxxKC, M58LRxxxKD
Signal descriptions
2
Signal descriptions
See Figure 1: Logic diagram and Table 1: Signal names for a brief overview of the signals connected to this device.
2.1
Address inputs (ADQ0-ADQ15 and A16-Amax)
Amax is the highest order address input. It is equal to A22 in the M58LR128KC/D and to A23 in the M58LR256KC/D. The address inputs select the cells in the memory array to access during bus read operations. During bus write operations they control the commands sent to the command interface of the Program/Erase Controller.
2.2
Data input/output (ADQ0-ADQ15)
The data I/O output the data stored at the selected address during a bus read operation or input a command or the data to be programmed during a bus write operation.
2.3
Chip Enable (E)
The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is at VILand Reset is at VIH the device is in active mode. When Chip Enable is at VIH the memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level.
2.4
Output Enable (G)
The Output Enable input controls data outputs during the bus read operation of the memory.
2.5
Write Enable (W)
The Write Enable input controls the bus write operation of the memory's command interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable, whichever occurs first.
2.6
Write Protect (WP)
Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is at VIL, the lock-down is enabled and the protection status of the lockeddown blocks cannot be changed. When Write Protect is at VIH, the lock-down is disabled and the locked-down blocks can be locked or unlocked. (Refer to Table 17: Lock status).
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Signal descriptions
M58LRxxxKC, M58LRxxxKD
2.7
Reset (RP)
The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in reset mode: the outputs are high impedance and the current consumption is reduced to the reset supply current IDD2. Refer to Table 22: DC characteristics - currents, for the value of IDD2. After Reset all blocks are in the locked state and the Configuration Register is reset. When Reset is at VIH, the device is in normal operation. Exiting reset mode the device enters asynchronous read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs.
2.8
Latch Enable (L)
Latch Enable latches the ADQ0-ADQ15 and A16-Amax address bits on its rising edge. The address latch is transparent when Latch Enable is at VIL and it is inhibited when Latch Enable is at VIH.
2.9
Clock (K)
The clock input synchronizes the memory to the microcontroller during synchronous read operations; the address is latched on a Clock edge (rising or falling, according to the configuration settings) when Latch Enable is at VIL. Clock is ignored during asynchronous read and in write operations.
2.10
Wait (WAIT)
Wait is an output signal used during synchronous read to indicate whether the data on the output bus are valid. This output is high impedance when Chip Enable is at VIH or Reset is at VIL. It can be configured to be active during the wait cycle or one clock cycle in advance. The WAIT signal is forced deasserted when Output Enable is at VIH.
2.11
VDD supply voltage
VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (read, program and erase).
2.12
VDDQ supply voltage
VDDQ provides the power supply to the I/O pins and enables all outputs to be powered independently from VDD. VDDQ can be tied to VDD or can use a separate supply.
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M58LRxxxKC, M58LRxxxKD
Signal descriptions
2.13
VPP program supply voltage
VPP is both a control input and a power supply pin. The two functions are selected by the voltage range applied to the pin. If VPP is kept in a low voltage range (0 V to VDDQ) VPP is seen as a control input. In this case a voltage lower than VPPLK gives absolute protection against program or erase, while VPP in the VPP1 range enables these functions (see Tables 22 and 23, DC Characteristics, for the relevant values). VPP is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. If VPP is in the range of VPPH it acts as a power supply pin. In this condition VPPF must be stable until the program/erase algorithm is completed.
2.14
VSS ground
VSS ground is the reference for the core supply. It must be connected to the system ground.
2.15
VSSQ ground
VSSQ ground is the reference for the input/output circuitry driven by VDDQ. VSSQ must be connected to VSS
Note:
Each device in a system should have VDD, VDDQ and VPP decoupled with a 0.1 F ceramic capacitor close to the pin (high-frequency, inherently-low inductance capacitors should be as close as possible to the package). See Figure 8: AC measurement load circuit. The PCB track widths should be sufficient to carry the required VPP program and erase currents.
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Bus operations
M58LRxxxKC, M58LRxxxKD
3
Bus operations
There are six standard bus operations that control the device. These are bus read, bus write, address latch, output disable, standby and reset. See Table 4: Bus operations, for a summary. Typically glitches of less than 5 ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus write operations.
3.1
Bus read
Bus read operations output the contents of the memory array, the electronic signature, the Status Register and the common Flash interface. Both Chip Enable and Output Enable must be at VIL to perform a read operation. The Chip Enable input should be used to enable the device, and Output Enable should be used to gate data onto the output. The data read depends on the previous command written to the memory (see Section 4: Command interface). See Figures 9, 10 and 11 Read AC Waveforms, and Tables 24 and 25 Read AC Characteristics, for details of when the output becomes valid.
3.2
Bus write
Bus write operations write commands to the memory or latch Input Data to be programmed. A bus write operation is initiated when Chip Enable and Write Enable are at VIL with Output Enable at VIH. Commands, Input Data and Addresses are latched on the rising edge of Write Enable or Chip Enable, whichever occurs first. The addresses must be latched prior to the write operation by toggling Latch Enable (when Chip Enable is at VIL). The Latch Enable must be tied to VIH during the bus write operation. See Figures 14 and 15, Write AC Waveforms, and Tables 26 and 27, Write AC Characteristics, for details of the timing requirements.
3.3
Address Latch
Address latch operations input valid addresses. Both Chip enable and Latch Enable must be at VIL during address latch operations. The addresses are latched on the rising edge of Latch Enable.
3.4
Output Disable
The outputs are high impedance when the Output Enable is at VIH.
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M58LRxxxKC, M58LRxxxKD
Bus operations
3.5
Standby
Standby disables most of the internal circuitry allowing a substantial reduction of the current consumption. The memory is in standby when Chip Enable and Reset are at VIH. The power consumption is reduced to the standby level IDD3 and the outputs are set to high impedance, independently from the Output Enable or Write Enable inputs. If Chip Enable switches to VIH during a program or erase operation, the device enters standby mode when finished.
3.6
Reset
During reset mode the memory is deselected and the outputs are high impedance. The memory is in reset mode when Reset is at VIL. The power consumption is reduced to the reset level, independently from the Chip Enable, Output Enable, or Write Enable inputs. If Reset is pulled to VSS during a program or erase, this operation is aborted and the memory content is no longer valid. Table 4. Bus operations(1)
E VIL VIL VIL VIL VIH X G VIL VIH VIH VIH X X W VIH VIL X VIH X X L VIH VIH VIL VIH X X RP VIH VIH VIH VIH VIH VIL Hi-Z Hi-Z WAIT(2) ADQ15-ADQ0 Data Output Data Input Address Input Hi-Z Hi-Z Hi-Z
Operation Bus Read Bus write Address Latch Output Disable Standby Reset
1. X = `don't care'
2. WAIT signal polarity is configured using the Set Configuration Register command.
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Command interface
M58LRxxxKC, M58LRxxxKD
4
Command interface
All bus write operations to the memory are interpreted by the command interface. Commands consist of one or more sequential bus write operations. An internal Program/Erase Controller manages all timings and verifies the correct execution of the program and erase commands. The Program/Erase Controller provides a Status Register, whose output may be read at any time to monitor the progress or the result of the operation. The command interface is reset to read mode when power is first applied, when exiting from reset or whenever VDD is lower than VLKO. Command sequences must be followed exactly. Any invalid combinations of commands are ignored. Refer to Table 5: Command codes, Table 6: Standard commands, Table 7: Factory commands, and Appendix D: Command interface state tables for a summary of the command interface. Table 5. Command codes
Command Block Lock Confirm Set Configuration Register Confirm Alternative Program Setup Block Erase Setup Block Lock-Down Confirm Program Setup Clear Status Register Block Lock Setup, Block Unlock Setup, Block Lock Down Setup and Set Configuration Register Setup Read Status Register Buffer Enhanced Factory Program Setup Read Electronic Signature Read CFI Query Program/Erase Suspend Blank Check Setup Protection Register Program Blank Check Confirm Program/Erase Resume, Block Erase Confirm, Block Unlock Confirm, Buffer Program or Buffer Enhanced Factory Program Confirm Buffer Program Read Array
Hex Code 01h 03h 10h 20h 2Fh 40h 50h 60h 70h 80h 90h 98h B0h BCh C0h CBh D0h E8h FFh
18/108
M58LRxxxKC, M58LRxxxKD
Command interface
4.1
Read Array command
The Read Array command returns the addressed bank to read array mode. One bus write cycle is required to issue the Read Array command. Once a bank is in read array mode, subsequent read operations output the data from the memory array. A Read Array command can be issued to any banks while programming or erasing in another bank. If the Read Array command is issued to a bank currently executing a program or erase operation, the bank returns to read array mode but the program or erase operation continues. However, the data output from the bank is not guaranteed until the program or erase operation has finished. The read modes of other banks are not affected.
4.2
Read Status Register command
The device contains a Status Register that monitors program or erase operations. The Read Status Register command reads the contents of the Status Register for the addressed bank. One bus write cycle is required to issue the Read Status Register command. Once a bank is in read Status Register mode, subsequent read operations output the contents of the Status Register. The Status Register data is latched on the falling edge of the Chip Enable or Output Enable signals. Either Chip Enable or Output Enable must be toggled to update the Status Register data. The Read Status Register command can be issued at any time, even during program or erase operations. The Read Status Register command only changes the read mode of the addressed bank. The read modes of other banks are not affected. Only asynchronous read and single synchronous read operations should be used to read the Status Register. A Read Array command is required to return the bank to read array mode. See Table 10 for the description of the Status Register bits.
4.3
Read Electronic Signature command
The Read Electronic Signature command reads the manufacturer and device codes, the lock status of the addressed bank, the Protection Register, and the Configuration Register. One bus write cycle is required to issue the Read Electronic Signature command. Once a bank is in read electronic signature mode, subsequent read operations in the same bank output the manufacturer code, the device code, the lock status of the addressed bank, the Protection Register, or the Configuration Register (see Table 8). The Read Electronic Signature command can be issued at any time, even during program or erase operations, except during Protection Register program operations. Dual operations between the parameter bank and the electronic signature location are not allowed (see Table 16: Dual operation limitations for details).
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Command interface
M58LRxxxKC, M58LRxxxKD
If a Read Electronic Signature command is issued to a bank that is executing a program or erase operation, the bank goes into read electronic signature mode. Subsequent bus read cycles output the electronic signature data and the Program/Erase Controller continues to program or erase in the background. The Read Electronic Signature command only changes the read mode of the addressed bank. The read modes of other banks are not affected. Only asynchronous read and single synchronous read operations should be used to read the electronic signature. A Read Array command is required to return the bank to read array mode.
4.4
Read CFI Query command
The Read CFI Query command reads data from the common Flash interface (CFI). One bus write cycle is required to issue the Read CFI Query command. Once a bank is in read CFI query mode, subsequent bus read operations in the same bank read from the common Flash interface. The Read CFI Query command can be issued at any time, even during program or erase operations. If a Read CFI Query command is issued to a bank that is executing a program or erase operation, the bank goes into read CFI query mode. Subsequent bus read cycles output the CFI data and the Program/Erase Controller continues to program or erase in the background. The Read CFI Query command only changes the read mode of the addressed bank; the read modes of other banks are not affected. Only asynchronous read and single synchronous read operations should be used to read from the CFI. A Read Array command is required to return the bank to read array mode. Dual operations between the parameter bank and the CFI memory space are not allowed (see Table 16: Dual operation limitations for details). See Appendix B: Common Flash interface and Tables 42, 43, 44, 45, 46, 47, 48, 49, 50 and 51 for details on the information contained in the common Flash interface memory area.
4.5
Clear Status Register command
The Clear Status Register command resets (set to `0') all error bits (SR1, 3, 4 and 5) in the Status Register. One bus write cycle is required to issue the Clear Status Register command. The Clear Status Register command does not affect the read mode of the bank. The error bits in the Status Register do not automatically return to `0' when a new command is issued. The error bits in the Status Register should be cleared before attempting a new program or erase command.
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M58LRxxxKC, M58LRxxxKD
Command interface
4.6
Block Erase command
The Block Erase command erases a block. It sets all the bits within the selected block to '1, and all previous data in the block is lost. If the block is protected then the erase operation aborts, the data in the block does not change, and the Status Register outputs the error. Two bus write cycles are required to issue the command:

The first bus cycle sets up the Block Erase command. The second latches the block address and starts the Program/Erase Controller.
If the second bus cycle is not the block erase confirm code, Status Register bits SR4 and SR5 are set and the command is aborted. Once the command is issued the bank enters read Status Register mode and any read operation within the addressed bank outputs the contents of the Status Register. A Read Array command is required to return the bank to read array mode. During block erase operations the bank containing the block being erased only accepts the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query, and the Program/Erase Suspend commands; all other commands are ignored. The block erase operation aborts if Reset, RP, goes to VIL. As data integrity cannot be guaranteed when the block erase operation is aborted, the block must be erased again. Refer to Section 8 for detailed information about simultaneous operations allowed in banks not being erased. Typical Erase times are given in Table 18: Program/erase times and endurance cycles. See Appendix C, Figure 21: Block erase flowchart and pseudocode for a suggested flowchart for using the Block Erase command.
4.7
Blank Check command
The Blank Check command checks whether a main array block has been completely erased. Only one block at a time can be checked. To use the Blank Check command VPP must be equal to VPPH. If VPP is not equal to VPPH, the device ignores the command and no error is shown in the Status Register. Two bus cycles are required to issue the Blank Check command:

The first bus cycle writes the Blank Check command (BCh) to any address in the block to be checked. The second bus cycle writes the Blank Check Confirm command (CBh) to any address in the block to be checked and starts the blank check operation.
If the second bus cycle is not Blank Check Confirm, Status Register bits SR4 and SR5 are set to '1' and the command aborts. Once the command is issued, the addressed bank automatically enters Status Register mode and further reads within the bank output the Status Register contents. The only operation permitted during blank check is read Status Register. Dual operations are not supported while a blank check operation is in progress. Blank check operations cannot be suspended and are not allowed while the device is in Program/Erase Suspend.
21/108
Command interface
M58LRxxxKC, M58LRxxxKD
The SR7 Status Register bit indicates the status of the blank check operation in progress. SR7 = '0' means that the blank check operation is still ongoing, and SR7 = '1' means that the operation is complete. The SR5 Status Register bit goes High (SR5 = '1') to indicate that the blank check operation has failed. At the end of the operation the bank remains in the read Status Register mode until another command is written to the command interface. See Appendix C, Figure 18: Blank check flowchart and pseudocode for a suggested flowchart for using the Blank Check command. Typical blank check times are given in Table 18: Program/erase times and endurance cycles.
4.8
Program command
The program command programs a single word to the memory array. If the block being programmed is protected, then the program operation will abort, the data in the block does not change and the Status Register outputs the error. Two bus write cycles are required to issue the Program command.

The first bus cycle sets up the Program command. The second latches the address and data to be programmed and starts the Program/Erase Controller.
Once the programming has started, read operations in the bank being programmed output the Status Register content. During a program operation, the bank containing the word being programmed only accepts the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query, and the Program/Erase Suspend commands; all other commands are ignored. A Read Array command is required to return the bank to read array mode. Refer to Section 8 for detailed information about simultaneous operations allowed in banks not being programmed. Typical program times are given in Table 18: Program/erase times and endurance cycles. The program operation aborts if Reset, RP, goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the word must be reprogrammed. See Appendix C, Figure 17: Program flowchart and pseudocode for the flowchart for using the Program command.
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M58LRxxxKC, M58LRxxxKD
Command interface
4.9
Buffer Program command
The Buffer Program command uses the device's 32-word write buffer to speed up programming. Up to 32 words can be loaded into the write buffer. The Buffer Program command dramatically reduces in-system programming time compared to the standard nonbuffered Program command. Four successive steps are required to issue the Buffer Program command: 1. The first bus write cycle sets up the Buffer Program command. The setup code can be addressed to any location within the targeted block. After the first bus write cycle, read operations in the bank output the contents of the Status Register. Status Register bit SR7 should be read to check that the buffer is available (SR7 = 1). If the buffer is not available (SR7 = 0), re-issue the Buffer Program command to update the Status Register contents. 2. The second bus write cycle sets up the number of words to be programmed. Value n is written to the same block address, where n+1 is the number of words to be programmed. Use n+1 bus write cycles to load the address and data for each word into the write buffer. Addresses must lie within the range from the start address to the start address + n, where the start address is the location of the first data to be programmed. Optimum performance is obtained when the start address corresponds to a 32-word boundary. The final bus write cycle confirms the Buffer Program command and starts the program operation.
3.
4.
All the addresses used in the buffer program operation must be within the same block. Address combinations that are invalid or that do not follow the correct bus write cycle sequence set an error in the Status Register and abort the operation without affecting the data in the memory array. If the block being programmed is protected an error is set in the Status Register and the operation aborts without affecting the data in the memory array. During buffer program operations the bank being programmed only accepts the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query, and Program/Erase Suspend commands; all other commands are ignored. Refer to Section 8 for detailed information about simultaneous operations allowed in banks not being programmed. See Appendix C, Figure 19: Buffer program flowchart and pseudocode for a suggested flowchart on using the Buffer Program command.
4.10
Buffer Enhanced Factory Program command
The Buffer Enhanced Factory Program command has been specially developed to speed up programming in manufacturing environments where the programming time is critical. It is used to program one or more write buffer(s) of 32 words to a block. Once the device enters buffer enhanced factory program mode, the write buffer can be reloaded any number of times as long as the address remains within the same block. Only one block can be programmed at a time.
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Command interface
M58LRxxxKC, M58LRxxxKD
If the block being programmed is protected, then the program operation aborts, the data in the block does not change, and the Status Register outputs the error. The use of the Buffer Enhanced Factory Program command requires certain operating conditions:

VPP must be set to VPPH VDD must be within operating range Ambient temperature TA must be 30C 10C The targeted block must be unlocked The start address must be aligned with the start of a 32-word buffer boundary The address must remain the start address throughout programming.
Dual operations are not supported during the Buffer Enhanced Factory program operation and the command cannot be suspended. The Buffer Enhanced Factory Program Command consists of three phases: the setup phase, the program and verify phase, and the exit phase. Refer to Table 7: Factory commands for detailed information.
4.10.1
Setup phase
The Buffer Enhanced Factory Program command requires two bus write cycles to initiate the command:

The first bus write cycle sets up the Buffer Enhanced Factory Program command. The second bus write cycle confirms the command.
After the confirm command is issued, read operations output the contents of the Status Register. The Read Status Register command must not be issued or it is interpreted as data to program. The Status Register P/EC Bit SR7 should be read to check that the P/EC is ready to proceed to the next phase. If an error is detected, SR4 goes high (set to `1') and the Buffer Enhanced Factory program operation is terminated. See Section 5: Status Register for details on the error.
4.10.2
Program and verify phase
The program and verify phase requires 32 cycles to program the 32 words to the write buffer. The data is stored sequentially, starting at the first address of the write buffer, until the write buffer is full (32 words). To program less than 32 words, the remaining words should be programmed with FFFFh. Three successive steps are required to issue and execute the program and verify phase of the command: 1. Use one bus write operation to latch the start address and the first word to be programmed. The Status Register bank write status bit SR0 should be read to check that the P/EC is ready for the next word.
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M58LRxxxKC, M58LRxxxKD 2.
Command interface
Each subsequent word to be programmed is latched with a new bus write operation. The address must remain the start address as the P/EC increments the address location.If any address is given that is not in the same block as the start address, the program and verify phase terminates. Status Register bit SR0 should be read between each bus write cycle to check that the P/EC is ready for the next word. Once the write buffer is full, the data is programmed sequentially to the memory array. After the program operation the device automatically verifies the data and reprograms if necessary.
3.
The program and verify phase can be repeated, without re-issuing the command, to program additional 32-word locations as long as the address remains in the same block. 4. Finally, after all words, or the entire block, have been programmed, write one bus write operation to any address outside the block containing the start address, to terminate program and verify phase.
Status Register bit SR0 must be checked to determine whether the program operation is finished. The Status Register may be checked for errors at any time but it must be checked after the entire block has been programmed.
4.10.3
Exit phase
Status Register P/EC bit SR7 set to `1' indicates that the device has exited the buffer enhanced factory program operation and returned to read Status Register mode. A full Status Register check should be done to ensure that the block has been successfully programmed. See tSection 5: Status Register for more details. For optimum performance the Buffer Enhanced Factory Program command should be limited to a maximum of 100 program/erase cycles per block. If this limit is exceeded the internal algorithm continues to work properly but some degradation in performance is possible. Typical program times are given in Table 18. See Appendix C, Figure 25: Buffer enhanced factory program flowchart and pseudocode for a suggested flowchart on using the Buffer Enhanced Factory Program command.
4.11
Program/Erase Suspend command
The Program/Erase Suspend command pauses a program or block erase operation. The command can be addressed to any bank. The Program/Erase Resume command is required to restart the suspended operation. One bus write cycle is required to issue the Program/Erase Suspend command. Once the Program/Erase Controller has paused bits SR7, SR6 and/ or SR2 of the Status Register is set to `1'. The following commands are accepted during program/erase suspend: - - - - - - Program/Erase Resume Read Array (data from erase-suspended block or program-suspended word is not valid) Read Status Register Read Electronic Signature Read CFI Query Clear Status Register
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Command interface
M58LRxxxKC, M58LRxxxKD
In addition, if the suspended operation was a block erase then the following commands are also accepted: - - - - - - Set Configuration Register Program (except in erase-suspended block) Buffer Program (except in erase suspended blocks) Block Lock Block Lock-Down Block Unlock.
During an erase suspend the block being erased can be protected by issuing the Block Lock or Block Lock-Down commands. When the Program/Erase Resume command is issued the operation completes. It is possible to accumulate multiple suspend operations. For example, it is possible to suspend an erase operation, start a program operation, suspend the program operation, and then read the array. If a Program command is issued during a block erase suspend, the erase operation cannot be resumed until the program operation has completed. The Program/Erase Suspend command does not change the read mode of the banks. If the suspended bank was in read Status Register, read electronic signature or read CFI query mode the bank remains in that mode and outputs the corresponding data. Refer to Section 8 for detailed information about simultaneous operations allowed during program/erase suspend. During a program/erase suspend, the device can be placed in standby mode by taking Chip Enable to VIH. Program/erase is aborted if Reset, RP, goes to VIL. See Appendix C, Figure 20: Program suspend and resume flowchart and pseudocode, and Figure 22: Erase suspend and resume flowchart and pseudocode for flowcharts for using the Program/Erase Suspend command.
4.12
Program/Erase Resume command
The Program/Erase Resume command restarts the program or erase operation suspended by the Program/Erase Suspend command. One bus write cycle is required to issue the command. The command can be issued to any address. The Program/Erase Resume command does not change the read mode of the banks. If the suspended bank was in read Status Register, read electronic signature or read CFI query mode the bank remains in that mode and outputs the corresponding data. If a Program command is issued during a block erase suspend, then the erase cannot be resumed until the program operation has completed. See Appendix C, Figure 20: Program suspend and resume flowchart and pseudocode, and Figure 22: Erase suspend and resume flowchart and pseudocode for flowcharts for using the Program/Erase Resume command.
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M58LRxxxKC, M58LRxxxKD
Command interface
4.13
Protection Register Program command
The Protection Register Program command programs the user one-time-programmable (OTP) segments of the Protection Register and the two Protection Register Locks. The device features 16 OTP segments of 128 bits and one OTP segment of 64 bits, as shown in Figure 4: Protection Register memory map. The segments are programmed one word at a time. When shipped, all bits in the segment are set to `1'. The user can only program the bits to `0'. Two bus write cycles are required to issue the Protection Register Program command:

The first bus cycle sets up the Protection Register Program command. The second latches the address and data to be programmed to the Protection Register and starts the Program/Erase Controller.
Read operations to the bank being programmed output the Status Register content after the program operation has started. Attempting to program a previously protected Protection Register results in a Status Register error. The Protection Register Program cannot be suspended. Dual operations between the parameter bank and the Protection Register memory space are not allowed (see Table 16: Dual operation limitations for details). The two Protection Register Locks protect the OTP segments from further modification. The protection of the OTP segments is not reversible. Refer to Figure 4: Protection Register memory map and Table 9: Protection Register locks for details on the lock bits. See Appendix C, Figure 24: Protection Register program flowchart and pseudocode for a flowchart for using the Protection Register Program command.
4.14
Set Configuration Register command
The Set Configuration Register command rewrites a new value to the Configuration Register. Two bus write cycles are required to issue the Set Configuration Register command:

The first cycle sets up the Set Configuration Register command and the address corresponding to the Configuration Register content. The second cycle writes the Configuration Register data and the confirm command.
The Configuration Register data must be written as an address during the bus write cycles, that is ADQ0 = CR0, ADQ1 = CR1, ..., ADQ15 = CR15. Addresses A16-Amax are ignored. Read operations output the array content after the Set Configuration Register command is issued. The Read Electronic Signature command is required to read the updated contents of the Configuration Register.
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Command interface
M58LRxxxKC, M58LRxxxKD
4.15
Block Lock command
The Block Lock command locks a block and prevents program or erase operations from changing the data in it. All blocks are locked after power-up or reset. Two bus write cycles are required to issue the Block Lock command:

The first bus cycle sets up the Block Lock command. The second bus write cycle latches the block address and locks the block.
The lock status can be monitored for each block using the Read Electronic Signature command. Table 17 shows the lock status after issuing a Block Lock command. Once set, the block lock bits remain set even after a hardware reset or power-down/powerup. They are cleared by a Block Unlock command. Refer to Section 9: Block locking, for a detailed explanation. See Appendix C, Figure 23: Locking operations flowchart and pseudocode for a flowchart for using the Lock command.
4.16
Block Unlock command
The Block Unlock command unlocks a block, allowing the block to be programmed or erased. Two bus write cycles are required to issue the Block Unlock command.

The first bus cycle sets up the Block Unlock command. The second bus write cycle latches the block address and unlocks the block.
The lock status can be monitored for each block using the Read Electronic Signature command. Table 17 shows the protection status after issuing a Block Unlock command. Refer to Section 9: Block locking for a detailed explanation and Appendix C, Figure 23: Locking operations flowchart and pseudocode for a flowchart for using the Block Unlock command.
4.17
Block Lock-Down command
The Block Lock-Down command locks down a locked or unlocked block. A locked-down block cannot be programmed or erased. The lock status of a locked-down block cannot be changed when WP is low, VIL. When WP is high, VIH, the lock-down function is disabled and the locked blocks can be individually unlocked by the Block Unlock command. Two bus write cycles are required to issue the Block Lock-Down command:

The first bus cycle sets up the Block Lock-Down command. The second bus write cycle latches the block address and locks-down the block.
The lock status can be monitored for each block using the Read Electronic Signature command. Locked-down blocks revert to the locked (and not locked-down) state when the device is reset on power-down. Table 17 shows the lock status after issuing a Block Lock-Down command.
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M58LRxxxKC, M58LRxxxKD
Command interface
Refer to Section 9: Block locking for a detailed explanation and Appendix C, Figure 23: Locking operations flowchart and pseudocode for a flowchart for using the Lock-Down command. Table 6. Standard commands(1)
Bus operations Cycles Commands 1st cycle Op. Read Array Read Status Register Read Electronic Signature Read CFI Query Clear Status Register Block Erase Program 1+ 1+ 1+ 1+ 1 2 2 Write Write Write Write Write Write Write Write Buffer Program(4) n+4 Write Write Program/Erase Suspend Program/Erase Resume Protection Register Program Set Configuration Register Block Lock Block Unlock Block Lock-Down 1 1 2 2 2 2 2 Write Write Write Write Write Write Write Add BKA BKA BKA BKA X BKA or BA(3) BKA or WA(3) BA PA1 PAn+1 X X PRA CRD BKA or BA(3) BKA or BA(3) BKA or BA(3) Data FFh 70h 90h 98h 50h 20h 40h or 10h E8h PD1 PDn+1 B0h D0h C0h 60h 60h 60h 60h Write Write Write Write Write PRA CRD BA BA BA PRD 03h 01h D0h 2Fh Write Write Write Write Write BA WA BA PA2 X D0h PD n PD2 D0h Op. Read Read Read Read 2nd cycle Add WA BKA(2) BKA
(2)
Data RD SRD ESD QD
BKA(2)
1. X = `don't care', WA = Word Address in targeted bank, RD = Read Data, SRD = Status Register Data, ESD = Electronic Signature Data, QD = Query Data, BA = Block Address, BKA = Bank Address, PD = Program Data, PRA = Protection Register Address, PRD = Protection Register Data, CRD = Configuration Register Data. 2. Must be same bank as in the first cycle. The signature addresses are listed in Table 8. 3. Any address within the bank can be used. 4. n+1 is the number of words to be programmed.
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Command interface Table 7. Factory commands
M58LRxxxKC, M58LRxxxKD
Bus write operations(1) Command Phase Cycles 1st Add Blank Check Setup 2 2 BA BKA or WA(2) WA1 NOT BA1(4) 2nd 3rd Final -1 Add Data Final Add Data
Data Add Data Add Data BCh 80h PD1 X BA WA1 WA1 CBh D0h PD2 WA1 PD3
Buffer Enhanced Program/ 32 Factory Verify(3) Program Exit 1
WA1 PD31 WA1 PD32
1. WA = Word Address in targeted bank, BKA = Bank Address, PD = Program Data, BA = Block Address, X = 'don't care'. 2. Any address within the bank can be used. 3. The program/verify phase can be executed any number of times as long as the data is to be programmed to the same block. 4. WA1 is the start address, NOT BA1 = not block address of WA1.
Table 8.
Electronic signature codes
Code Address (h) Bank address + 00 Top Bank address + 01 Bank address + 01 Data (h) 0020 882Eh (M58LR128KC) 881Ch (M58LR256KC) 882Fh (M58LR128KD) 881Dh (M58LR256KD) 0001 0000 Block address + 02 Locked and locked-down Unlocked and locked-down 0003 0002 Bank address + 05 Bank address + 80 OTP area permanently locked Bank address + 81 Bank address + 84 0000 Unique device number OTP area PRLD(1) OTP area CR(1) 0002
Manufacturer code
Device code Bottom Locked Unlocked Block protection
Configuration Register Protection Register PR0 lock Numonyx factory default
Protection Register PR0 Bank address + 85 Bank address + 88 Protection Register PR1 through PR16 lock Protection Registers PR1-PR16 Bank address + 89 Bank address + 8A Bank address + 109
1. CR = Configuration Register, PRLD = Protection Register Lock Data
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M58LRxxxKC, M58LRxxxKD Figure 4. Protection Register memory map
PROTECTION REGISTERS
Command interface
109h
PR16
User Programmable OTP
102h
91h
PR1
User Programmable OTP
8Ah Protection Register Lock 89h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
88h 85h 84h
PR0 User Programmable OTP
Unique device number 81h 80h Protection Register Lock 10
AI07563
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Command interface Table 9. Protection Register locks
Lock
M58LRxxxKC, M58LRxxxKD
Description Number Address Bits Bit 0 Lock 1 80h Bit 1 Preprogrammed to protect unique device number, address 81h to 84h in PR0 Protects 64 bits of OTP segment, address 85h to 88h in PR0
Bits 2 to 15 Reserved Bit 0 Bit 1 Bit 2 ---Lock 2 89h Protects 128 bits of OTP segment PR1 Protects 128 bits of OTP segment PR2 Protects 128 bits of OTP segment PR3 ---Protects 128 bits of OTP segment PR14 Protects 128 bits of OTP segment PR15 Protects 128 bits of OTP segment PR16
Bit 13 Bit 14 Bit 15
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M58LRxxxKC, M58LRxxxKD
Status Register
5
Status Register
The Status Register provides information on the current or previous program or erase operations. Issue a Read Status Register command to read the contents of the Status Register (refer to Section 4.2: Read Status Register command for more details). To output the contents, the Status Register is latched and updated on the falling edge of the Chip Enable or Output Enable signals and can be read until Chip Enable or Output Enable returns to VIH. The Status Register can only be read using single asynchronous or single synchronous reads. Bus read operations from any address within the bank always read the Status Register during program and erase operations. The various bits convey information about the status and any errors of the operation. Bits SR7, SR6, SR2 and SR0 give information on the status of the device and are set and reset by the device. Bits SR5, SR4, SR3 and SR1 give information on errors, they are set by the device but must be reset by issuing a Clear Status Register command or a hardware reset. If an error bit is set to `1' the Status Register should be reset before issuing another command. The bits in the Status Register are summarized in Table 10: Status Register bits. Refer to Table 10 in conjunction with the descriptions in the following sections.
5.1
Program/Erase Controller status bit (SR7)
The Program/Erase Controller status bit indicates whether the Program/Erase Controller is active or inactive in any bank. When the Program/Erase Controller status bit is Low (set to `0'), the Program/Erase Controller is active. When the bit is High (set to `1'), the Program/Erase Controller is inactive, and the device is ready to process a new command. The Program/Erase Controller status bit is Low immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller pauses. After the Program/Erase Controller pauses the bit is High.
5.2
Erase suspend status bit (SR6)
The erase suspend status bit indicates that an erase operation has been suspended in the addressed block. When the erase suspend status bit is High (set to `1'), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. The erase suspend status bit should only be considered valid when the Program/Erase Controller status bit is High (Program/Erase Controller inactive). SR6 is set within the erase suspend latency time of the Program/Erase Suspend command being issued, therefore, the memory may still complete the operation rather than entering the suspend mode. When a Program/Erase Resume command is issued the erase suspend status bit returns Low.
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Status Register
M58LRxxxKC, M58LRxxxKD
5.3
Erase/blank check status bit (SR5)
The erase/blank check status bit identifies if there was an error during a block erase operation. When the erase/blank check status bit is High (set to `1'), the Program/Erase Controller has applied the maximum number of pulses to the block and still failed to verify that it has erased correctly. The erase/blank check status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). The erase/blank check status bit also indicates whether an error occurred during the blank check operation. If the data at one or more locations in the block where the blank check command has been issued is different from FFFFh, SR5 is set to '1'. Once set High, the erase/blank check status bit must be set Low by a Clear Status Register command or a hardware reset before a new erase command is issued, otherwise the new command appears to fail.
5.4
Program status bit (SR4)
The program status bit identifies if there was an error during a program operation. The program status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). When the program status bit is High (set to `1'), the Program/Erase Controller has applied the maximum number of pulses to the word and still failed to verify that it has programmed correctly. Attempting to program a '1' to an already programmed bit while VPP = VPPH also sets the Program Status bit High. If VPP is different from VPPH, SR4 remains Low (set to '0') and the attempt is not shown. Once set High, the program status bit must be set Low by a Clear Status Register command or a hardware reset before a new program command is issued, otherwise the new command appears to fail.
5.5
VPP status bit (SR3)
The VPP status bit identifies an invalid voltage on the VPP pin during program and erase operations. The VPP pin is only sampled at the beginning of a program or erase operation. Program and erase operations are not guaranteed if VPP becomes invalid during an operation When the VPP status bit is Low (set to `0'), the voltage on the VPP pin was sampled at a valid voltage. When the VPP status bit is High (set to `1'), the VPP pin has a voltage that is below the VPP lockout voltage, VPPLK, the memory is protected and program and erase operations cannot be performed. Once set High, the VPP status bit must be set Low by a Clear Status Register command or a hardware reset before a new program or erase command is issued, otherwise the new command appears to fail.
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M58LRxxxKC, M58LRxxxKD
Status Register
5.6
Program suspend status bit (SR2)
The program suspend status bit indicates that a program operation has been suspended in the addressed block. The program suspend status bit should only be considered valid when the Program/Erase Controller status bit is High (Program/Erase Controller inactive). When the program suspend status bit is High (set to `1'), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. SR2 is set within the program suspend latency time of the Program/Erase Suspend command being issued, therefore, the memory may still complete the operation rather than entering the suspend mode. When a Program/Erase Resume command is issued, the program suspend status bit returns Low.
5.7
Block protection status bit (SR1)
The block protection status bit identifies if a program or block erase operation has tried to modify the contents of a locked or locked-down block. When the block protection status bit is High (set to `1'), a program or erase operation has been attempted on a locked or locked-down block Once set High, the block protection status bit must be set Low by a Clear Status Register command or a hardware reset before a new program or erase command is issued, otherwise the new command appears to fail.
5.8
Bank write/multiple word program status bit (SR0)
The bank write status bit indicates whether the addressed bank is programming or erasing. In buffer enhanced factory program mode the multiple word program bit shows if the device is ready to accept a new word to be programmed to the memory array. The bank write status bit should only be considered valid when the Program/Erase Controller status bit SR7 is Low (set to `0'). When both the Program/Erase Controller status bit and the bank write status bit are Low (set to `0'), the addressed bank is executing a program or erase operation. When the Program/Erase Controller status bit is Low (set to `0') and the bank write status bit is High (set to `1'), a program or erase operation is being executed in a bank other than the one being addressed. In buffer enhanced factory program mode if the multiple word program status bit is Low (set to `0'), the device is ready for the next word. If the multiple word program status bit is High (set to `1') the device is not ready for the next word. For further details on how to use the Status Register, see the flowcharts and pseudocodes provided in Appendix C.
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Status Register Table 10.
Bit
M58LRxxxKC, M58LRxxxKD Status Register bits
Name Type Logic Level(1) '1' Ready Busy Erase suspended Erase In progress or completed Erase/blank check error Erase/blank check success Program error Program success VPP invalid, abort VPP OK Program suspended Program in progress or completed Program/erase on protected block, abort No operation to protected blocks SR7 = `1' Not allowed '1' SR7 = `0' Bank write status Status SR7 = `1' '0' SR7 = `0' Program or erase operation in addressed bank Program or erase operation in a bank other than the addressed bank No program or erase operation in the device Definition
SR7 P/EC status
Status '0' '1'
SR6 Erase suspend status Status '0' SR5 Erase/blank check status '1' Error '0' '1' SR4 Program status Error '0' '1' SR3 VPP status Program suspend status Block protection status Error '0' '1' Status '0' '1' Error '0'
SR2
SR1
SR0 '1' Multiple word program status (buffer enhanced factory program mode) Status
SR7 = `1' Not allowed The device is not ready for the next SR7 = `0' buffer loading or is going to exit the BEFP mode. SR7 = `1' '0' SR7 = `0' The device is ready for the next buffer loading. The device has exited the BEFP mode.
1. Logic level '1' is High, '0' is Low.
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M58LRxxxKC, M58LRxxxKD
Configuration Register
6
Configuration Register
The Configuration Register configures the type of bus access that the memory performs. Refer to Section 7: Read modes for details on read operations. The Configuration Register is set through the command interface using the Set Configuration Register command. After a reset or power-up the device is configured for asynchronous read (CR15 = 1). The Configuration Register bits are described in Table 12 They specify the selection of the burst length, burst type, burst X latency and the read operation. Refer to Figures 5 and 6 for examples of synchronous burst configurations.
6.1
Read select bit (CR15)
The read select bit, CR15, switches between asynchronous and synchronous read operations. When the read select bit is set to '1', read operations are asynchronous, and when the read select bit is set to '0', read operations are synchronous. Synchronous burst read is supported in both parameter and main blocks and can be performed across banks. On reset or power-up the read select bit is set to '1' for asynchronous access.
6.2
X latency bits (CR13-CR11)
The X latency bits are used during synchronous read operations to set the number of clock cycles between the address being latched and the first data becoming available. Refer to Figure 5: X latency and data output configuration example. For correct operation the X latency bits can only assume the values in Table 12: Configuration Register. Table 11 shows how to set the X latency parameter, taking into account the speed class of the device and the frequency used to read the Flash memory in synchronous mode. Table 11. X latency settings
fmax 30 MHz 40 MHz 54 MHz 66 MHz 86 MHz tKmin 33 ns 25 ns 19 ns 15 ns 12 ns X latency min 2 3 4 4 6
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Configuration Register
M58LRxxxKC, M58LRxxxKD
6.3
Wait polarity bit (CR10)
The wait polarity bit sets the polarity of the Wait signal used in synchronous burst read mode. During synchronous burst read mode the Wait signal indicates whether the data output are valid or a WAIT state must be inserted. When the wait polarity bit is set to `0' the Wait signal is active Low. When the wait polarity bit is set to `1' the Wait signal is active High.
6.4
Data output configuration bit (CR9)
The data output configuration bit configures the output to remain valid for either one or two clock cycles during synchronous mode. When the data output configuration bit is '0' the output data is valid for one clock cycle, and when the data output configuration bit is '1' the output data is valid for two clock cycles. The data output configuration bit must be configured using the following condition:
tK > tKQV + tQVK_CPU tK is the clock period tQVK_CPU is the data setup time required by the system CPU tKQV is the clock to data valid time.
where

If this condition is not satisfied, the data output configuration bit should be set to `1' (two clock cycles). Refer to Figure 5: X latency and data output configuration example.
6.5
Wait configuration bit (CR8)
The wait configuration bit controls the timing of the Wait output pin, WAIT, in synchronous burst read mode. When WAIT is asserted, data is not valid and when WAIT is deasserted, data is valid. When the wait configuration bit is Low (set to '0') the Wait output pin is asserted during the WAIT state. When the wait configuration bit is High (set to '1'), the Wait output pin is asserted one data cycle before the WAIT state.
6.6
Burst type bit (CR7)
The burst type bit determines the sequence of addresses read during synchronous burst reads. It is High (set to '1'), as the memory outputs from sequential addresses only. See Table 13: Burst type definition for the sequence of addresses output from a given starting address in sequential mode.
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M58LRxxxKC, M58LRxxxKD
Configuration Register
6.7
Valid clock edge bit (CR6)
The valid clock edge bit, CR6, configures the active edge of the Clock, K, during synchronous read operations. When the valid clock edge bit is Low (set to '0') the falling edge of the Clock is the active edge. When the valid clock edge bit is High (set to '1') the rising edge of the Clock is the active edge.
6.8
Wrap burst bit (CR3)
The wrap burst bit, CR3, selects between wrap and no wrap. Synchronous burst reads can be confined inside the 4, 8 or 16-word boundary (wrap) or overcome the boundary (no wrap). When the wrap burst bit is Low (set to `0') the burst read wraps. When it is High (set to `1') the burst read does not wrap.
6.9
Burst length bits (CR2-CR0)
The burst length bits set the number of words to be output during a synchronous burst read operation as result of a single address latch cycle. They can be set for 4 words, 8 words, 16 words or continuous burst, where all the words are read sequentially. In continuous burst mode the burst sequence can cross bank boundaries. In continuous burst mode, in 4, 8 or 16 words no-wrap, depending on the starting address, the device asserts the WAIT signal to indicate that a delay is necessary before the data is output. If the starting address is shifted by 1, 2 or 3 positions from the four-word boundary, WAIT is asserted for 1, 2 or 3 clock cycles, respectively, when the burst sequence crosses the first 16-word boundary, to indicate that the device needs an internal delay to read the successive words in the array. WAIT will be asserted only once during a continuous burst access. See also Table 13: Burst type definition. CR14, CR5 and CR4 are reserved for future use.
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Configuration Register Table 12.
Bit CR15 CR14
M58LRxxxKC, M58LRxxxKD Configuration Register
Description Read select 1 Reserved 010 011 100 2 clock latency(1) 3 clock latency 4 clock latency 5 clock latency 6 clock latency 7 clock latency (default) Asynchronous read (default at power-on) Value 0 Synchronous read Description
CR13-CR11
X latency
101 110 111
Other configurations reserved 0 CR10 Wait polarity 1 0 CR9 Data output configuration 1 0 CR8 Wait configuration 1 0 CR7 Burst type 1 0 CR6 CR5-CR4 CR3 Valid clock edge 1 Reserved 0 Wrap burst 1 001 010 CR2-CR0 Burst length 011 111 16 words Continuous (default) No wrap (default) 4 words 8 words Wrap Rising Clock edge (default) Sequential (default) Falling Clock edge WAIT is active High Data held for one clock cycle Data held for two clock cycles (default)(1) WAIT is active during WAIT state (default) WAIT is active one data cycle before WAIT state(1) Reserved WAIT is active Low (default)
1. The combination X latency=2, data held for two clock cycles and Wait active one data cycle before the WAIT state is not supported.
40/108
M58LRxxxKC, M58LRxxxKD Table 13.
Mode Start Add 0 1 2 3 Wrap ... 7 ... 12 13 14 15 7-4-5-6 7-0-1-2-3-4-56 7-8-9-10-11-12-13-1415-0-1-2-3-4-5-6
Configuration Register
Burst type definition
4 words Sequential 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 8 words Sequential 0-1-2-3-4-5-67 1-2-3-4-5-6-70 2-3-4-5-6-7-01 16 words Continuous burst Sequential 0-1-2-3-4-5-6-7-8-9-1011-12-13-14-15 1-2-3-4-5-6-7-8-9-1011-12-13-14-15-0 2-3-4-5-6-7-8-9-10-1112-13-14-15-0-1 0-1-2-3-4-5-6... 1-2-3-4-5-6-7-...15-WAIT-16-1718... 2-3-4-5-6-7...15-WAIT-WAIT-1617-18... 3-4-5-6-7...15-WAIT-WAITWAIT-16-17-18...
3-4-5-6-7-0-1- 3-4-5-6-7-8-9-10-11-122 13-14-15-0-1-2
7-8-9-10-11-12-13-14-15-WAITWAIT-WAIT-16-17...
12-13-14-15-16-17-18... 13-14-15-WAIT-16-17-18... 14-15-WAIT-WAIT-16-17-18.... 15-WAIT-WAIT-WAIT-16-17-18...
41/108
Configuration Register Table 13.
Mode Start Add 0
M58LRxxxKC, M58LRxxxKD Burst type definition (continued)
4 words Sequential 0-1-2-3 8 words Sequential 0-1-2-3-4-5-67 1-2-3-4-5-6-78 2-3-4-5-6-7-89... 3-4-5-6-7-8-910 16 words Continuous burst Sequential 0-1-2-3-4-5-6-7-8-9-1011-12-13-14-15 1-2-3-4-5-6-7-8-9-1011-12-13-14-15-WAIT16 2-3-4-5-6-7-8-9-10-1112-13-14-15-WAITWAIT-16-17 3-4-5-6-7-8-9-10-11-1213-14-15-WAIT-WAITWAIT-16-17-18
1
1-2-3-4
2
2-3-4-5
3 ... 7 ... 12
3-4-5-6
No-wrap
7-8-9-10
7-8-9-10-1112-13-14
7-8-9-10-11-12-13-1415-WAIT-WAIT-WAIT16-17-18-19-20-21-22
Same as for wrap (wrap /no wrap has no effect on continuous burst)
12-13-1415 13-14-15WAIT-16 14-15WAITWAIT-1617 15-WAITWAITWAIT-1617-18
12-13-14-1516-17-18-19 13-14-15WAIT-16-1718-19-20 14-15-WAITWAIT-16-1718-19-20-21 15-WAITWAIT-WAIT16-17-18-1920-21-22
12-13-14-15-16-17-1819-20-21-22-23-24-2526-27 13-14-15-WAIT-16-1718-19-20-21-22-23-2425-26-27-28 14-15-WAIT-WAIT-1617-18-19-20-21-22-2324-25-26-27-28-29 15-WAIT-WAIT-WAIT16-17-18-19-20-21-2223-24-25-26-27-28-2930
13
14
15
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M58LRxxxKC, M58LRxxxKD Figure 5. X latency and data output configuration example
X-latency 1st cycle K 2nd cycle 3rd cycle 4th cycle
Configuration Register
E
L
Amax-A16(1)
VALID ADDRESS tQVK_CPU tKQV tK
ADQ15-ADQ0 VALID ADDRESS VALID DATA VALID DATA
AI12321b
1. Amax is equal to A22 in the M58LR128KC/D and, to A23 in the M58LR256KC/D. 2. The settings shown are X-latency = 4, data output held for one clock cycle.
43/108
Configuration Register Figure 6.
E
M58LRxxxKC, M58LRxxxKD
Wait configuration example
K
L
G
Amax-A16(1)
VALID ADDRESS
ADQ15-ADQ0
VALID ADDRESS
VALID DATA VALID DATA
NOT VALID
VALID DATA
WAIT CR8 = '0' CR10 = '0' WAIT CR8 = '1' CR10 = '0' WAIT CR8 = '0' CR10 = '1' WAIT CR8 = '1' CR10 = '1'
AI12322b
1. Amax is equal to A22 in the M58LR128KC/D and, to A23 in the M58LR256KC/D.
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M58LRxxxKC, M58LRxxxKD
Read modes
7
Read modes
Read operations can be performed in two different ways depending on the settings in the Configuration Register. If the clock signal is `don't care' for the data output, the read operation is asynchronous. If the data output is synchronized with clock, the read operation is synchronous. The read mode and format of the data output are determined by the Configuration Register (see Section 6: Configuration Register for details). All banks support both asynchronous and synchronous read operations.
7.1
Asynchronous read mode
In asynchronous read operations the clock signal is `don't care'. The device outputs the data corresponding to the address latched, that is the memory array, Status Register, common Flash interface or electronic signature depending on the command issued. CR15 in the Configuration Register must be set to `1' for asynchronous operations. The device features an automatic standby mode. During asynchronous read operations, after a bus inactivity of 150 ns, the device automatically switches to the automatic standby mode. In this condition the power consumption is reduced to the standby value and the outputs are still driven. In asynchronous read mode, the WAIT signal is always de-asserted. See Table 24: Asynchronous read AC characteristics and Figure 9: Asynchronous random access read AC waveforms for details.
7.2
Synchronous burst read mode
In synchronous burst read mode the data is output in bursts synchronized with the clock. It is possible to perform burst reads across bank boundaries. Synchronous burst read mode can only be used to read the memory array. For other read operations, such as read Status Register, read CFI and read electronic signature, single synchronous read or asynchronous random access read must be used. In synchronous burst read mode the flow of the data output depends on parameters that are configured in the Configuration Register. A burst sequence starts at the first clock edge (rising or falling depending on valid clock edge bit CR6 in the Configuration Register) after the falling edge of Latch Enable or Chip Enable, whichever occurs last. Addresses are internally incremented and data is output on each data cycle after a delay which depends on the X latency bits CR13-CR11 of the Configuration Register. The number of words to be output during a synchronous burst read operation can be configured as 4 words, 8 words, 16 words or continuous (burst length bits CR2-CR0). The data can be configured to remain valid for one or two clock cycles (data output configuration bit CR9). The order of the data output can be modified through the wrap burst bit in the Configuration Register. The burst sequence is sequential and can be confined inside the 4, 8 or 16 word boundary (wrap) or overcome the boundary (no wrap).
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Read modes
M58LRxxxKC, M58LRxxxKD
The WAIT signal may be asserted to indicate to the system that an output delay occurs. This delay depends on the starting address of the burst sequence and on the burst configuration. WAIT is asserted during the X latency, the WAIT state and at the end of a 4, 8 and 16-word burst. It is only deasserted when output data are valid or when G is at VIH. In continuous burst read mode a WAIT state occurs when crossing the first 16-word boundary. If the starting address is aligned to the burst length (4, 8 or 16 words) the wrapped configuration has no impact on the output sequence. The WAIT signal can be configured to be active Low or active High by setting CR10 in the Configuration Register. See Table 25: Synchronous read AC characteristics and Figure 10: Synchronous burst read AC waveforms for details.
7.2.1
Synchronous burst read suspend
A synchronous burst read operation can be suspended, freeing the data bus for other higher priority devices. It can be suspended during the initial access latency time (before data is output) or after the device has output data. When the synchronous burst read operation is suspended, internal array sensing continues and any previously latched internal data is retained. A burst sequence can be suspended and resumed as often as required as long as the operating conditions of the device are met. A synchronous burst read operation is suspended when Chip Enable, E, is Low and the current address has been latched (on a Latch Enable rising edge or on a valid clock edge). The Clock signal is then halted at VIH or at VIL, and Output Enable, G, goes High. When Output Enable, G, becomes Low again and the Clock signal restarts, the synchronous burst read operation is resumed exactly where it stopped. WAIT, being gated by E, becomes deasserted and does not revert to high impedance when G goes High. Therefore, if two or more devices are connected to the system's READY signal, to prevent bus contention the WAIT signal of the M58LRxxxKC/D should not be directly connected to the system's READY signal. WAIT will revert to high-impedance when Chip Enable, E, goes High. See Table 25: Synchronous read AC characteristics and Figure 12: Synchronous burst read suspend AC waveforms for details.
7.3
Single synchronous read mode
Single synchronous read operations are similar to synchronous burst read operations except that the memory outputs the same data to the end of the operation. Synchronous single reads are used to read the electronic signature, Status Register, CFI, block protection status, Configuration Register Status or Protection Register. When the addressed bank is in read CFI, read Status Register or read electronic signature mode, the WAIT signal is deasserted when Output Enable, G, is at VIH or for the one clock cycle during which output data is valid. Otherwise, it is asserted. See Table 25: Synchronous read AC characteristics and Figure 11: Single synchronous read AC waveforms for details.
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M58LRxxxKC, M58LRxxxKD
Dual operations and multiple bank architecture
8
Dual operations and multiple bank architecture
The multiple bank architecture of the M58LRxxxKC/D gives greater flexibility for software developers to split the code and data spaces within the memory array. The dual operations feature simplifies the software management of the device by allowing code to be executed from one bank while another bank is being programmed or erased. The dual operations feature means that while programming or erasing in one bank, read operations are possible in another bank with zero latency (only one bank at a time is allowed to be in program or erase mode). If a read operation is required in a bank, which is programming or erasing, the program or erase operation can be suspended. Also, if the suspended operation is erase then a program command can be issued to another block, so the device can have one block in erase suspend mode, one programming, and other banks in read mode. Bus read operations are allowed in another bank between setup and confirm cycles of program or erase operations. By using a combination of these features, read operations are possible at any moment in the M58LRxxxKC/D device. Dual operations between the parameter bank and either of the CFI, the OTP or the electronic signature memory space are not allowed. Table 16 shows which dual operations are allowed or not between the CFI, the OTP, the electronic signature locations and the memory array. Tables 14 and 15 show the dual operations possible in other banks and in the same bank. Table 14. Dual operations allowed in other banks
Commands allowed in another bank Status of bank Read Array Yes Yes Yes Yes Yes Read Read Read Status CFI Electronic Register Query Signature Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Program, Buffer Program Yes - - - Yes Block Erase Yes - - - - Program Program /Erase /Erase Suspend Resume Yes Yes Yes - - Yes - - Yes Yes
Idle Programming Erasing Program suspended Erase suspended
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Dual operations and multiple bank architecture Table 15.
Status of bank
M58LRxxxKC, M58LRxxxKD
Dual operations allowed in same bank
Commands allowed in same bank Read Array Yes -
(1) (1)
Read Read Status CFI Register Query Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Read Electronic Signature Yes Yes Yes Yes Yes
Program, Buffer Program Yes - - - Yes(2)
Block Erase Yes - - - -
Program Program /Erase /Erase Suspend Resume Yes Yes Yes - - Yes - - Yes Yes
Idle Programming Erasing Program suspended Erase suspended
-
Yes(2) Yes(2)
1. The Read Array command is accepted but the data output is not guaranteed until the program or erase has completed. 2. Not allowed in the block that is being erased or in the word that is being programmed.
Table 16.
Dual operation limitations
Commands allowed Read main blocks
Current status
Read CFI/OTP/ electronic signature
Read parameter blocks
Located in parameter bank No
Not located in parameter bank Yes
Programming/erasing parameter blocks Located in parameter bank
No
No
Yes
No
No
Yes
Programming / erasing main Not located in blocks parameter bank Programming OTP
Yes No
Yes No
Yes No
In different bank only No
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M58LRxxxKC, M58LRxxxKD
Block locking
9
Block locking
The M58LRxxxKC/D features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. This locking scheme has three levels of protection.

Lock/unlock - this first level allows software only control of block locking. Lock-down - this second level requires hardware interaction before locking can be changed. VPP VPPLK - the third level offers complete hardware protection against program and erase on all blocks.
The protection status of each block can be set to locked, unlocked, and locked-down. Table 17 defines all of the possible protection states (WP, ADQ1, ADQ0), and Appendix C Figure 23 shows a flowchart for the locking operations.
9.1
Reading a block's lock status
The lock status of every block can be read in the read electronic signature mode of the device. To enter this mode issue the Read Electronic Signature command. Subsequent reads at the address specified in Table 8 output the protection status of that block. The lock status is represented by ADQ0 and ADQ1. ADQ0 indicates the block lock/unlock status and is set by the Lock command and cleared by the Unlock command. ADQ0 is automatically set when entering lock-down. ADQ1 indicates the lock-down status and is set by the Lock-Down command. ADQ1 cannot be cleared by software, only by a hardware reset or power-down. The following sections explain the operation of the locking system.
9.2
Locked state
The default status of all blocks on power-up or after a hardware reset is locked (states (0,0,1) or (1,0,1)). Locked blocks are fully protected from program or erase operations. Any program or erase operations attempted on a locked block return an error in the Status Register. The status of a locked block can be changed to unlocked or locked-down using the appropriate software commands. An unlocked block can be locked by issuing the Lock command.
9.3
Unlocked state
Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)) can be programmed or erased. All unlocked blocks return to the locked state after a hardware reset or when the device is powered-down. The status of an unlocked block can be changed to locked or locked-down using the appropriate software commands. A locked block can be unlocked by issuing the Unlock command.
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Block locking
M58LRxxxKC, M58LRxxxKD
9.4
Lock-down state
Blocks that are locked-down (state (0,1,x)) are protected from program and erase operations (as for locked blocks) but their protection status cannot be changed using software commands alone. A locked or unlocked block can be locked down by issuing the Lock-Down command. Locked-down blocks revert to the locked state when the device is reset or powered-down. The lock-down function is dependent on the Write Protect, WP, input pin. When WP=0 (VIL), the blocks in the lock-down state (0,1,x) are protected from program, erase and protection status changes. When WP=1 (VIH) the lock-down function is disabled (1,1,x) and locked-down blocks can be individually unlocked to the (1,1,0) state by issuing the software command, where they can be erased and programmed. When the lock-down function is disabled (WP=1) blocks can be locked (1,1,1) and unlocked (1,1,0) as desired. When WP=0 blocks that were previously locked-down return to the lockdown state (0,1,x) regardless of any changes that were made while WP=1. Device reset or power-down resets all blocks, including those in lock-down, to the locked state.
9.5
Locking operations during erase suspend
Changes to the block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock or lock-down a block. This is useful in the case when another block needs to be updated while an erase operation is in progress. To change block locking during an erase operation, first write the Erase Suspend command, then check the Status Register until it indicates that the erase operation has been suspended. Next, write the desired lock command sequence to a block and the lock status is changed. After completing any desired lock, read, or program operations, resume the erase operation with the Erase Resume command. If a block is locked or locked down during an erase suspend of the same block, the locking status bits change immediately. But when the erase is resumed, the erase operation completes. Locking operations cannot be performed during a program suspend.
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M58LRxxxKC, M58LRxxxKD Table 17. Lock status
Next protection status(1) (WP, ADQ1, ADQ0) After Block Lock command 1,0,1 1,0,1 1,1,1 1,1,1 0,0,1 0,0,1 0,1,1 After Block Unlock command 1,0,0 1,0,0 1,1,0 1,1,0 0,0,0 0,0,0 0,1,1 After Block Lock-Down command 1,1,1 1,1,1 1,1,1 1,1,1 0,1,1 0,1,1 0,1,1
Block locking
Current protection status(1) (WP, ADQ1, ADQ0) Current state 1,0,0 1,0,1
(2)
Program/erase allowed yes no yes no yes no no
After WP transition 0,0,0 0,0,1 0,1,1 0,1,1 1,0,0 1,0,1 1,1,1 or 1,1,0(3)
1,1,0 1,1,1 0,0,0 0,0,1
(2)
0,1,1
1. The lock status is defined by the write protect pin and by ADQ1 (`1' for a locked-down block) and ADQ0 (`1' for a locked block) as read in the Read Electronic Signature command with ADQ1 = VIH and ADQ0 = VIL. 2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status. 3. A WP transition to VIH on a locked block restores the previous ADQ0 value, giving a 111 or 110.
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Program and erase times and endurance cycles
M58LRxxxKC, M58LRxxxKD
10
Program and erase times and endurance cycles
The program and erase times and the number of program/erase cycles per block are shown in Table 18. Exact erase times may change depending on the memory array condition. The best case is when all the bits in the block are at `0' (pre-programmed). The worst case is when all the bits in the block are at `1' (not preprogrammed). Usually, the system overhead is negligible with respect to the erase time. In the M58LRxxxKC/D the maximum number of program/erase cycles depends on the VPP voltage supply used.
Table 18.
Program/erase times and endurance cycles(1) (2)
Condition Parameter block (16 KWord) Min Typ 0.4 1.2 1.5 12 12 384 768 20 20 100 000 100 000 25 25 Typical after 100 kW/E cycles 1 3 Max 2.5 4 4 180 180 Unit s s s s s s ms s s cycles cycles
Parameter
Erase
Main block (64 KWord) Single word
Preprogrammed Not preprogrammed Word program
VPP = VDD
Program(3)
Buffer program Buffer (32 words) (buffer program) Main block (64 KWord) Program
Suspend latency Erase Program/erase cycles (per block) Main blocks Parameter blocks
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M58LRxxxKC, M58LRxxxKD Table 18.
Program and erase times and endurance cycles
Program/erase times and endurance cycles(1) (2) (continued)
Condition Parameter block (16 KWord) Min Typ 0.4 1 10 2.5 80 80 160 160 1.28 1.28 1000 2500 16 4 Typical after 100 kW/E cycles Max 2.5 4 170 Unit s s s s s s ms ms s s cycles cycles ms ms
Parameter
Erase Main block (64 KWord) Word program Single word Buffer enhanced factory program(4) Buffer program Buffer (32 words) VPP = VPPH Program
(3)
Buffer enhanced factory program Buffer program
Main block (64 KWords)
Buffer enhanced factory program Buffer program
Bank (8 Mbits)
Buffer enhanced factory program
Program/erase cycles (per block) Blank check
Main blocks Parameter blocks Main blocks Parameter blocks
1. TA = -25 to 85C; VDD = 1.7 V to 2 V; VDDQ = 1.7 V to 2 V. 2. Values are liable to change with the external system-level overhead (command sequence and Status Register polling execution). 3. Excludes the time needed to execute the command sequence. 4. This is an average value on the entire device.
53/108
Maximum ratings
M58LRxxxKC, M58LRxxxKD
11
Maximum ratings
Stressing the device above the rating listed in Table 19 may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to Absolute maximum rating conditions for extended periods may affect device reliability. Refer to the Numonyx SURE program and other relevant quality documents. Table 19.
Symbol TA TBIAS TSTG VIO VDD VDDQ VPP IO tVPPH
Absolute maximum ratings
Value Parameter Min Ambient operating temperature Temperature under bias Storage temperature Input or output voltage Supply voltage Input/output supply voltage Program voltage Output short circuit current Time for VPP at VPPH -25 -25 -65 -0.5 -0.2 -0.2 -0.2 Max 85 85 125 VDDQ + 0.6 2.45 2.45 10 100 100 C C C V V V V mA hours Unit
54/108
M58LRxxxKC, M58LRxxxKD
DC and AC parameters
12
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables in this section are derived from tests performed under the measurement conditions summarized in Table 20: Operating and AC measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 20. Operating and AC measurement conditions
Parameter VDD supply voltage VDDQ supply voltage VPP supply voltage (factory environment) VPP supply voltage (application environment) Ambient operating temperature Load capacitance (CL) Input rise and fall times Input pulse voltages Input and output timing ref. voltages 0 to VDDQ VDDQ/2 Min 1.7 1.7 8.5 -0.4 -25 30 5 Max 2.0 2.0 9.5 VDDQ+0.4 85 Units V V V V C pF ns V V
Figure 7.
AC measurement I/O waveform
VDDQ VDDQ/2 0V
AI06161
55/108
DC and AC parameters Figure 8. AC measurement load circuit
VDDQ
M58LRxxxKC, M58LRxxxKD
VDDQ VDD 16.7k DEVICE UNDER TEST 0.1F 0.1F CL 16.7k
CL includes JIG capacitance
AI06162
Table 21.
Symbol CIN COUT
Capacitance(1)
Parameter Input capacitance Output capacitance Test condition VIN = 0 V VOUT = 0 V Min 6 8 Max 8 12 Unit pF pF
1. Sampled only, not 100% tested.
56/108
M58LRxxxKC, M58LRxxxKD Table 22.
Symbol ILI ILO
DC and AC parameters
DC characteristics - currents
Parameter Input leakage current Output leakage current Supply current asynchronous read (f = 5 MHz) Test condition 0V VIN VDDQ 0V VOUT VDDQ E = VIL, G = VIH 4 word Supply current synchronous read (f = 66 MHz) 8 word 16 word Continuous 4 word Supply current synchronous read (f = 86 MHz) 8 word 16 word Continuous M58LR128KC/D 13 18 20 22 24 22 25 30 33 22 50 22 50 22 50 10 20 10 20 33 Typ Max 1 1 15 20 22 24 26 25 27 32 35 70 A M58LR256KC/D M58LR128KC/D M58LR256KC/D M58LR128KC/D 70 70 A 70 70 A M58LR256KC/D 70 30 34 30 34 49 mA mA mA mA mA Unit A A mA mA mA mA mA mA mA mA mA
IDD1
IDD2
Supply current (reset)
RP = VSS 0.2 V E = VDD 0.2 V K = VSS E = VIL, G = VIH
IDD3
Supply current (standby)
IDD4
Supply current (automatic standby)
Supply current (program) IDD5(1) Supply current (erase)
VPP = VPPH VPP = VDD VPP = VPPH VPP = VDD Program/erase in one bank, asynchronous read in another bank Program/erase in one bank, synchronous read (continuous f = 66 MHz) in another bank E = VDD 0.2 V K = VSS M58LR128KC/D M58LR256KC/D
Supply current IDD6(1),(2) (dual operations)
44 22 50 2 0.2 2 0.2 0.2 0.2
60 50
mA
IDD7(1)
Supply current program/ erase suspended (standby) VPP supply current (program)
A 70 5 5 5 5 5 5 mA A mA A A A
VPP = VPPH VPP = VDD VPP = VPPH VPP = VDD VPP VDD VPP VDD
IPP1(1) VPP supply current (erase) IPP2 IPP3(1) VPP supply current (read) VPP supply current (standby)
1. Sampled only, not 100% tested. 2. VDD dual operation current is the sum of read and program or erase currents.
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DC and AC parameters Table 23.
Symbol VIL VIH VOL VOH VPP1 VPPH VPPLK VLKO
M58LRxxxKC, M58LRxxxKD
DC characteristics - voltages
Parameter Input low voltage Input high voltage Output low voltage Output high voltage VPP program voltage-logic VPP program voltage factory Program or erase lockout VDD lock voltage IOL = 100 A IOH = -100 A Program, erase Program, erase VDDQ -0.1 1.3 8.5 1.8 9.0 3.3 9.5 0.4 1 Test condition Min 0 VDDQ -0.4 Typ Max 0.4 VDDQ + 0.4 0.1 Unit V V V V V V V V
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tAVQV ADQ0-ADQ15 VALID DATA VALID ADDRESS Hi-Z
M58LRxxxKC, M58LRxxxKD Figure 9.
A16-Amax(1) VALID ADDRESS tAVAV tAVLH L tLLLH tLLQV tELLH E tELQV tEHQZ tEHQX G tGLQV tGLQX tELTV WAIT(2) Hi-Z tGHQX tLHGL tLHAX
VALID
Asynchronous random access read AC waveforms
tGHQZ tEHTZ
Valid Address Latch
Outputs Enabled
Data Valid
Standby
DC and AC parameters
Notes: 1. Amax is equal to A22 in the M58LR128KC/D and, to A23 in the M58LR256KC/D 2. Write Enable, W, is High, WAIT is active Low.
59/108
AI13798b
DC and AC parameters Table 24.
Symbol tAVAV tAVQV tELTV tELQV(2) Read Timings tEHTZ tEHQX(1) tEHQZ
(1)
M58LRxxxKC, M58LRxxxKD Asynchronous read AC characteristics
Alt tRC tACC Parameter Address Valid to Next Address Valid Address Valid to Output Valid (Random) Chip Enable Low to Wait Valid tCE Chip Enable Low to Output Valid Chip Enable High to Wait Hi-Z tOH tHZ tOE tOLZ tOH tDF tAVADVH tELADVH tADVHAX Chip Enable High to Output Transition Chip Enable High to Output Hi-Z Output Enable Low to Output Valid Output Enable Low to Output Transition Output Enable High to Output Transition Output Enable High to Output Hi-Z Address Valid to Latch Enable High Chip Enable Low to Latch Enable High Latch Enable High to Address Transition Min Max Max Max Max Min Max Max Min Min Max Min Min Min Min Max Min 86 MHz 66 MHz Unit 70 70 9 70 11 0 11 20 0 0 11 4 9 4 7 70 4 70 70 11 70 14 0 14 20 0 0 14 7 10 5 7 70 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tGLQV(2) tGLQX(1) tGHQX
(1)
tGHQZ(1) tAVLH Latch Timings tELLH tLHAX tLLLH tLLQV tLHGL
tADVLADVH Latch Enable Pulse Width tADVLQV tADVHGL Latch Enable Low to Output Valid (Random) Latch Enable High to Output Enable Low
1. Sampled only, not 100% tested. 2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV.
60/108
M58LRxxxKC, M58LRxxxKD
ADQ0-ADQ15
VALID ADDRESS
VALID
VALID
VALID
NOT VALID
VALID
A16-Amax(4)
VALID ADDRESS
tAVLH tLLLH
L tEHQX tKHQV Note 1 tKHAX tEHEL tKHQX tEHQZ
tLLKH
tAVKH
K
tELKH
E tGLQV tGLQX tGHQX tGHQZ
Figure 10. Synchronous burst read AC waveforms
G tKHTV tGLTV Note 2 X Latency Valid Data Flow Note 2 tKHTX Note 2 Boundary Crossing Standby tEHTZ
tELTV
Hi-Z
WAIT
Address Latch
DC and AC parameters
Note 1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register. 2. The WAIT signal can be configured to be active during wait state or one cycle before. WAIT signal is active Low. 3. Address latched and data output on the rising clock edge. 4. Amax is equal to A22 in the M58LR128KC/D and to A23 in the M58LR256KC/D.
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AI13799b
62/108
VALID NOT VALID NOT VALID NOT VALID NOT VALID NOT VALID tEHQX tKHQV Note 1 tKHAX tEHEL tEHQZ
DC and AC parameters
ADQ0-ADQ15
VALID ADDRESS
A16-Amax(4)
VALID ADDRESS
tAVLH
tLLLH
L
tLLKH
tAVKH
K(3)
tELKH
E tGLQX tGLQV tGHQX tGHQZ
Figure 11. Single synchronous read AC waveforms
G tELTV tGLTV tKHTV tGHTV tEHTZ
Hi-Z
WAIT(2)
M58LRxxxKC, M58LRxxxKD
Note 1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register. 2. The WAIT signal is configured to be active during wait state. WAIT signal is active Low. 3. Address latched and data output on the rising clock edge. 4. Amax is equal to A22 in the M58LR128KC/D and, to A23 in the M58LR256KC/D.
AI13800b
M58LRxxxKC, M58LRxxxKD
ADQ0-ADQ15
VALID ADDRESS
VALID
VALID
VALID
VALID
A16-Amax(5)
VALID ADDRESS
tAVLH tLLLH
L tEHQX tKHQV Note 1 Note 3 tEHEL tEHQZ
tLLKH
tAVKH
K(4)
tELKH
tKHAX
E tGLQX tGLQV tGHQZ tGLQV tGHQX tGHQZ
G tGLTV tEHTZ
Figure 12. Synchronous burst read suspend AC waveforms
tELTV
Hi-Z
WAIT(2)
DC and AC parameters
Note 1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register. 2. The WAIT signal is configured to be active during wait state. WAIT signal is active Low. 3. The CLOCK signal can be held high or low 4. Address latched and data output on the rising clock edge. 5. Amax is equal to A22 in the M58LR128KC/D and to A23 in the M58LR256KC/D.
AI13801b
63/108
DC and AC parameters Figure 13. Clock input AC waveform
tKHKL
M58LRxxxKC, M58LRxxxKD
tKHKH
tf
tr
tKLKH
AI06981
Table 25.
Symbol tAVKH tELKH tELTV Synchronous Read Timings tEHEL tEHTZ tGHTV tGLTV tKHAX tKHQV tKHTV tKHQX tKHTX tLLKH Clock Specifications tKHKH(3) tKHKL tKLKH tf tr
Synchronous read AC characteristics(1) (2)
Alt tAVCLKH tELCLKH Parameter Address Valid to Clock High Chip Enable Low to Clock High Chip Enable Low to Wait Valid Chip Enable Pulse Width (subsequent synchronous reads) Chip Enable High to Wait Hi-Z Output Enable High to Wait Valid Output Enable Low to Wait Valid tCLKHAX tCLKHQV tCLKHQX Clock High to Address Transition Clock High to Output Valid Clock High to WAIT Valid Clock High to Output Transition Clock High to WAIT Transition Min Min Max Min Max Min Max Min Max 86 MHz 4 4 9 11 11 11 11 6 9 66 MHz 5 5 11 14 14 11 11 7 11 Unit ns ns ns ns ns ns ns ns ns
Min Min Min
2 4
3 5 15
ns ns ns
tADVLCLKH Latch Enable Low to Clock High tCLK Clock Period (f = 66 MHz) Clock Period (f = 86 MHz) Clock High to Clock Low Clock Low to Clock High Clock Fall or Rise Time
12 Min 3.5 3.5 ns
Max
3
3
ns
1. Sampled only, not 100% tested. 2. For other timings please refer to Table 24: Asynchronous read AC characteristics. 3. The device can support jitters of +/-5% on clock frequency.
64/108
PROGRAM OR ERASE tAVAV BANK ADD. tLHAX BANK ADDRESS VALID ADDRESS VALID ADDRESS tWHDX COMMAND VALID ADD. CMD OR DATA VALID ADD. STATUS REGISTER tAVAV
ADQ0-ADQ15
A16-Amax(1) tAVLH tLLLH tDVWH
M58LRxxxKC, M58LRxxxKD
L tELLH tWHLL tELLH tELQV tLHGL
E tELWL tWHEH
G tGHLL tWLWH tWHEL
Figure 14. Write AC waveforms, write enable controlled
W tWHWL tWPHWH tWHWPL tQVWPL
WP tWHVPL
VPP tVPHWH tWHKH tQVVPL
K SET-UP COMMAND CONFIRM COMMAND STATUS REGISTER READ 1ST POLLING
Ai13802c
DC and AC parameters
65/108
Note 1: Amax is equal to A22 in the M58LR128KC/D and to A23 in the M58LR256KC/D.
DC and AC parameters Table 26.
Symbol tAVAV tAVLH tDVWH tELLH Write Enable Controlled Timings tELWL tELQV tGHLL tLHAX tLHGL tLLLH tWHDX tWHEH tWHEL(2) tWHKH(2) tWHLL
(2)
M58LRxxxKC, M58LRxxxKD Write AC characteristics, write enable controlled(1)
Alt tWC Parameter Address Valid to Next Address Valid Address Valid to Latch Enable High tDS Data Valid to Write Enable High Chip Enable Low to Latch Enable High tCS Chip Enable Low to Write Enable Low Chip Enable Low to Output Valid Output Enable High to Latch Enable Low Latch Enable High to Address Transition Latch Enable High to Output Enable Low Latch Enable Pulse Width tDH tCH Write Enable High to Input Transition Write Enable High to Chip Enable High Write Enable High to Chip Enable Low Write Enable High to Clock High Write Enable High to Latch Enable Low tWPH tWP Write Enable High to Write Enable Low Write Enable Low to Write Enable High Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min 86 MHz 66 MHz 70 4 40 9 0 70 14 4 4 7 0 0 25 35 25 25 40 0 0 200 200 200 200 70 7 40 10 0 70 20 5 5 7 0 0 25 35 25 25 45 0 0 200 200 200 200 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tWHWL tWLWH tQVVPL Protection Timings tQVWPL tVPHWH tWHVPL tWHWPL tWPHWH
Output (Status Register) Valid to VPP Low Min Output (Status Register) Valid to Write Protect Low tVPS VPP High to Write Enable High Write Enable High to VPP Low Write Enable High to Write Protect Low Write Protect High to Write Enable High Min Min Min Min Min
1. Sampled only, not 100% tested. 2. tWHEL , tWHLL, and tWHKH have the values shown when reading in the targeted bank or when reading following a Set Configuration Register command.System designers should take this into account and may insert a software No-Op instruction to delay the first read in the same bank after issuing any command and to delay the first read to any address after issuing a Set Configuration Register command. If the first read after the command is a Read Array operation in a different bank and no changes to the Configuration Register have been issued, tWHEL and tWHLL are 0 ns, whilst tWHKH is equal to tELKH.
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PROGRAM OR ERASE tAVAV BANK ADD tLHAX BANK ADDRESS tAVLH tLLLH VALID ADDRESS VALID ADDRESS tDVEH tEHDX COMMAND VALID ADD CMD OR DATA VALID ADD STATUS REGISTER tAVAV
ADQ0-ADQ15
M58LRxxxKC, M58LRxxxKD
A16-Amax(1)
L tELLH tEHLL tELLH tLHGL
E tELEH tWLEL tEHEL tELQV
G tGHLL tEHWH tWHEL
Figure 15. Write AC waveforms, chip enable controlled
W tEHWPL tWPHEH tQVWPL
WP tEHVPL tVPHEH tQVVPL
VPP tEHKH
K SET-UP COMMAND CONFIRM COMMAND STATUS REGISTER READ 1ST POLLING
Ai13803c
DC and AC parameters
67/108
Note 1: Amax is equal to A22 in the M58LR128KC/D and to A23 in the M58LR256KC/D.
DC and AC parameters Table 27.
Symbol tAVAV tAVLH tDVEH tEHDX Chip Enable Controlled Timings tEHEL
(2) (2)
M58LRxxxKC, M58LRxxxKD Write AC characteristics, chip enable controlled(1)
Alt tWC Parameter Address Valid to Next Address Valid Address Valid to Latch Enable High tDS tDH Data Valid to Chip Enable High Chip Enable High to Input Transition Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min 86 MHz 66 MHz Unit 70 4 40 0 25 35 0 0 40 9 70 14 4 4 7 25 0 200 200 0 0 200 200 70 7 40 0 25 35 0 0 45 10 70 20 5 5 7 25 0 200 200 0 0 200 200 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tWPH Chip Enable High to Chip Enable Low Chip Enable High to Clock High Chip Enable High to Latch Enable Low tCH tWP Chip Enable High to Write Enable High Chip Enable Low to Chip Enable High Chip Enable Low to Latch Enable High Chip Enable Low to Output Valid Output Enable High to Latch Enable Low Latch Enable High to Address Transition Latch Enable High to Output Enable Low Latch Enable Pulse Width Write Enable High to Chip Enable Low tCS Write Enable Low to Chip Enable Low Chip Enable High to VPP Low Chip Enable High to Write Protect Low Output (Status Register) Valid to VPP Low Output (Status Register) Valid to Write Protect Low tVPS VPP High to Chip Enable High Write Protect High to Chip Enable High
tEHKH
tEHLL tEHWH tELEH tELLH tELQV tGHLL tLHAX tLHGL tLLLH tWHEL(2) tWLEL tEHVPL
Protection Timings 68/108
tEHWPL tQVVPL tQVWPL tVPHEH tWPHEH
1. Sampled only, not 100% tested. 2. tWHEL, tEHEL , and tEHKH have the values shown when reading in the targeted bank or when reading following a Set Configuration Register command.System designers should take this into account and may insert a software No-Op instruction to delay the first read in the same bank after issuing any command and to delay the first read to any address after issuing a Set Configuration Register command. If the first read after the command is a Read Array operation in a different bank and no changes to the Configuration Register have been issued, tWHEL and tEHEL are 0 ns, whilst tEHKH is equal to tELKH.
M58LRxxxKC, M58LRxxxKD Figure 16. Reset and power-up AC waveforms
DC and AC parameters
W, E, G, L
tPHWL tPHEL tPHGL tPHLL
tPLWL tPLEL tPLGL tPLLL
RP tVDHPH VDD, VDDQ Power-Up Reset
AI06976
tPLPH
Table 28.
Symbol tPLWL tPLEL tPLGL tPLLL tPHWL tPHEL tPHGL tPHLL tPLPH(1),(2) tVDHPH(3)
Reset and power-up AC characteristics
Parameter Reset Low to Write Enable Low, Chip Enable Low, Output Enable Low, Latch Enable Low Reset High to Write Enable Low Chip Enable Low Output Enable Low Latch Enable Low RP pulse width Supply voltages High to Reset High Test condition During program During erase Other conditions Min Min Min 25 25 80 Unit s s ns
Min
30
ns
Min Min
50 300
ns s
1. The device Reset is possible but not guaranteed if tPLPH < 50 ns. 2. Sampled only, not 100% tested. 3. It is important to assert RP in order to allow proper CPU initialization during power-up or reset.
69/108
Part ordering information
M58LRxxxKC, M58LRxxxKD
13
Part ordering information
Table 29.
Example: Device type M58 Architecture L = multilevel, multiple bank, burst mode Operating voltage R = VDD = 1.7 V to 2.0 V, VDDQ = 1.7 V to 2.0 V Density 128 = 128 Mbit (x16) 256 = 256 Mbit (x16) Technology K = 65 nm technology Parameter location C = top boot, mux I/O D = bottom boot, mux I/O Speed 76 = 70 ns, 66 Mhz speed class 78 = 70 ns, 86 MHz speed class Package Not packaged separately(1) Temperature range 5 = -25 to 85 C
1. The M58LRxxxKC/D are only available as part of a multichip package
Ordering information scheme
M58LR256KD 76 5
Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (speed, package, etc.), for daisy chain ordering information or for further information on any aspect of this device, please contact the Numonyx sales office nearest to you.
70/108
M58LRxxxKC, M58LRxxxKD
Block address tables
Appendix A
Block address tables
The following set of equations can be used to calculate a complete set of block addresses for the M58LRxxxKC/D using the information contained in Tables 33 to 41. To calculate the block base address from the block number: First it is necessary to calculate the bank number and the block number offset. This can be achieved using the following formulas: Bank_Number = (Block_Number -3) / 8 Block_Number_Offset = Block_Number -3 -(Bank_Number x 8), If Bank_Number= 0, the block base address can be directly read from Tables 33 and 39 (parameter bank block addresses) in the address range column, in the row that corresponds to the given block number. Otherwise: Block_Base_Address = Bank_Base_Address + Block_Base_Address_Offset To calculate the bank number and the block number from the block base address: If the address is in the range of the parameter bank, the bank number is 0 and the block number can be directly read from Tables 33 and 39 (parameter bank block addresses), in the block number column, in the row that corresponds to the address given. Otherwise, the block number can be calculated using the formulas below: For the top configuration (M58LR256KC and M58LR128KC): Block_Number = ((NOT address) / 216) + 3 For the bottom configuration (M58LR256KD and M58LR128KD): Block_Number = (address / 216) + 3 For both configurations the bank number and the block number offset can be calculated using the following formulas: Bank_Number = (Block_Number -3) / 8 Block_Number_Offset = Block_Number - 3 -(Bank_Number x 8)
71/108
Block address tables Table 30.
M58LRxxxKC, M58LRxxxKD M58LR128KC - parameter bank block addresses
Size (KWords) 16 16 16 16 64 64 64 64 64 64 64 Address range 7FC000-7FFFFF 7F8000-7FBFFF 7F4000-7F7FFF 7F0000-7F3FFF 7E0000-7EFFFF 7D0000-7DFFFF 7C0000-7CFFFF 7B0000-7BFFFF 7A0000-7AFFFF 790000-79FFFF 780000-78FFFF
Block number 0 1 2 3 4 5 6 7 8 9 10
Table 31.
M58LR128KC - main bank base addresses
Block numbers 11-18 19-26 27-34 35-42 43-50 51-58 59-66 67-74 75-82 83-90 91-98 99-106 107-114 115-122 123-130 Bank base address 70 0000 68 0000 60 0000 58 0000 50 0000 48 0000 40 0000 38 0000 30 0000 28 0000 20 0000 18 0000 10 0000 08 0000 00 0000
Bank number(1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1. There are two bank regions: bank region 1 contains all the banks that are made up of main blocks only; bank region 2 contains the banks that are made up of the parameter and main blocks (Parameter Bank).
72/108
M58LRxxxKC, M58LRxxxKD Table 32. M58LR128KC - block addresses in main banks
Block address tables
Block number offset 0 1 2 3 4 5 6 7
Block base address offset 07 0000 06 0000 05 0000 04 0000 03 0000 02 0000 01 0000 00 0000
Table 33.
M58LR256KC - parameter bank block addresses
Size (KWords) 16 16 16 16 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 Address range FFC000-FFFFFF FF8000-FFBFFF FF4000-FF7FFF FF0000-FF3FFF FE0000-FEFFFF FD0000-FDFFFF FC0000-FCFFFF FB0000-FBFFFF FA0000-FAFFFF F90000-F9FFFF F80000-F8FFFF F70000-F7FFFF F60000-F6FFFF F50000-F5FFFF F40000-F4FFFF F30000-F3FFFF F20000-F2FFFF F10000-F1FFFF F00000-F0FFFF
Block number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
73/108
Block address tables Table 34. M58LR256KC - main bank base addresses
Block numbers 19-34 35-50 51-66 67-82 83-98 99-114 115-130 131-146 147-162 163-178 179-194 195-210 211-226 227-242 243-258
M58LRxxxKC, M58LRxxxKD
Bank number(1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Bank base address E00000 D00000 C00000 B00000 A00000 900000 800000 700000 600000 500000 400000 300000 200000 100000 000000
1. There are two bank regions: bank region 1 contains all the banks that are made up of main blocks only; bank region 2 contains the banks that are made up of the parameter and main blocks (parameter bank).
Table 35.
M58LR256KC - block addresses in main banks
Block base address offset 0F0000 0E0000 0D0000 0C0000 0B0000 0A0000 090000 080000 070000 060000 050000 040000 030000 020000 010000 000000
Block number offset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
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M58LRxxxKC, M58LRxxxKD Table 36. M58LR128KD - parameter bank block addresses
Size (KWords) 64 64 64 64 64 64 64 16 16 16 16
Block address tables
Block number 10 9 8 7 6 5 4 3 2 1 0
Address range 070000-07FFFF 060000-06FFFF 050000-05FFFF 040000-04FFFF 030000-03FFFF 020000-02FFFF 010000-01FFFF 00C000-00FFFF 008000-00BFFF 004000-007FFF 000000-003FFF
75/108
Block address tables Table 37. M58LR128KD - main bank base addresses
Block numbers 123-130 115-122 107-114 99-106 91-98 83-90 75-82 67-74 59-66 51-58 43-50 35-42 27-34 19-26 11-18
M58LRxxxKC, M58LRxxxKD
Bank number(1) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Bank base address 78 0000 70 0000 68 0000 60 0000 58 0000 50 0000 48 0000 40 0000 38 0000 30 0000 28 0000 20 0000 18 0000 10 0000 08 0000
1. There are two bank regions: bank region 2 contains all the banks that are made up of main blocks only; bank region 1 contains the banks that are made up of the parameter and main blocks (parameter bank).
Table 38.
M58LR128KD - block addresses in main banks
Block base address offset 070000 060000 050000 040000 030000 020000 010000 000000
Block number offset 7 6 5 4 3 2 1 0
76/108
M58LRxxxKC, M58LRxxxKD Table 39. M58LR256KD - parameter bank block addresses
Size (KWords) 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 16 16 16 16
Block address tables
Block number 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Address range 0F0000-0FFFFF 0E0000-0EFFFF 0D0000-0DFFFF 0C0000-0CFFFF 0B0000-0BFFFF 0A0000-0AFFFF 090000-09FFFF 080000-08FFFF 070000-07FFFF 060000-06FFFF 050000-05FFFF 040000-04FFFF 030000-03FFFF 020000-02FFFF 010000-01FFFF 00C000-00FFFF 008000-00BFFF 004000-007FFF 000000-003FFF
77/108
Block address tables Table 40. M58LR256KD - main bank base addresses
Block numbers 243-258 227-242 211-226 195-210 179-194 163-178 147-162 131-146 115-130 99-114 83-98 67-82 51-66 35-50 19-34
M58LRxxxKC, M58LRxxxKD
Bank number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Bank base address F00000 E00000 D00000 C00000 B00000 A00000 900000 800000 700000 600000 500000 400000 300000 200000 100000
1. There are two bank regions: bank region 2 contains all the banks that are made up of main blocks only; bank region 1 contains the banks that are made up of the parameter and main blocks (parameter bank).
Table 41.
M58LR256KD - block addresses in main banks
Block base address offset 0F0000 0E0000 0D0000 0C0000 0B0000 0A0000 090000 080000 070000 060000 050000 040000 030000 020000 010000 000000
Block number offset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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M58LRxxxKC, M58LRxxxKD
Common Flash interface
Appendix B
Common Flash interface
The common Flash interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary. When the Read CFI Query Command is issued the device enters CFI query mode and the data structure is read from the memory. Tables 42, 43, 44, 45, 46, 47, 48, 49, 50 and 51 show the addresses used to retrieve the data. The query data is always presented on the lowest order data outputs (ADQ0-ADQ7), and the other outputs (ADQ8-ADQ15) are set to 0. The CFI data structure also contains a security area where a 64-bit unique security number is written (see Figure 4: Protection Register memory map). This area can be accessed only in read mode by the final user. It is impossible to change the security number after it has been written by Numonyx. Issue a Read Array command to return to read mode. Table 42.
Offset 000h 010h 01Bh 027h P A Reserved CFI Query identification string System interface information Device geometry definition
Query structure overview
Sub-section name Description Reserved for algorithm-specific information Command set ID and algorithm data offset Device timing and voltage information Flash device layout
Primary algorithm-specific extended query Additional information specific to the primary table algorithm (optional) Alternate algorithm-specific extended query table Security code area Additional information specific to the alternate algorithm (optional) Lock Protection Register Unique device number and user programmable OTP
080h
1. The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections detailed in Tables 43, 44, 45 and 46. Query data is always presented on the lowest order data outputs.
79/108
Common Flash interface Table 43.
Offset 000h
M58LRxxxKC, M58LRxxxKD
CFI query identification string
Sub-section name 0020h 882Eh 882Fh 881Ch 881Dh Reserved 0051h 0052h 0059h 0001h 0000h Offset = P = 000Ah 0001h 0000h 0000h Value = A = 0000h Address for alternate algorithm extended query table NA 0000h Primary algorithm command set and control interface ID code 16-bit ID code defining a specific algorithm Address for primary algorithm extended query table (see Table 46) Alternate vendor command set and control Interface ID code second vendor - specified algorithm supported p = 10Ah Query unique ASCII string "QRY" Manufacturer code M58LR128KC M58LR128KD M58LR256KC M58LR256KD Description Value Numonyx Top Bottom
001h
Device code
002h-00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah
Reserved "Q" "R" "Y"
NA
80/108
M58LRxxxKC, M58LRxxxKD Table 44.
Offset
Common Flash interface
CFI query system interface information
Data Description VDD logic supply minimum program/erase or write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts VDD logic supply maximum program/erase or write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts VPP [programming] supply minimum program/erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts VPP [programming] supply maximum program/erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts Typical timeout per single byte/word program = 2n s Typical timeout for buffer program = 2 s Typical timeout per individual block erase = Typical timeout for full chip erase = 2n ms Maximum timeout for word program = 2 times typical Maximum timeout for buffer program = 2n times typical
n n n
Value
01Bh
0017h
1.7 V
01Ch
0020h
2V
01Dh
0085h
8.5 V
01Eh 01Fh 020h 021h 022h 023h 024h 025h 026h
0095h 0004h 0009h 000Ah 0000h 0004h 0004h 0002h 0000h
9.5 V 16 s 512 s
2n
ms
1s NA 256 s 8192 s 4s NA
Maximum timeout per individual block erase = 2 times typical Maximum timeout for chip erase = 2n times typical
81/108
Common Flash interface Table 45.
Offset 027h 0019h 028h 029h 02Ah 02Bh 02Ch 0001h 0000h 0006h 0000h 0002h 007Eh 0000h 00FEh 0000h 0000h 0002h 0003h 0000h 0080h 0000h
M58LRxxxKC, M58LRxxxKD
Device geometry definition
Data 0018h Description M58LR128KC/D device size = 2n in number of bytes M58LR256KC/D device size = 2 in number of bytes Flash device interface code description Maximum number of bytes in multi-byte program or page = 2n Number of identical sized erase block regions within the device bit 7 to 0 = x = number of erase block regions M58LR128KC/D erase block region 1 information Number of identical-size erase blocks = 007Eh+1 M58LR256KC/D erase block region 1 information Number of identical-size erase blocks = 00FEh+1 Erase block region 1 information Block size in region 1 = 0200h * 256 bytes Erase block region 2 information Number of identical-size erase blocks = 0003h+1 Erase block region 2 information Block size in region 2 = 0080h * 256 bytes
n
Value 16 Mbytes 32 Mbytes x16 async. 64 bytes
2
127 255 128 KByte 4 32 KByte NA 4 32 KBytes 127 255 128 KBytes NA
02Dh 02Eh TOP DEVICES
02Fh 030h 031h 032h 033h 034h 035h 038h 02Dh 02Eh 02Fh 030h
Reserved Reserved for future erase block region information 0003h 0000h 0080h 0000h 007Eh 0000h 00FEh 0000h 0000h 0002h Erase block region 1 information Number of identical-size erase block = 0003h+1 Erase block region 1 information Block size in region 1 = 0080h * 256 bytes M58LR128KC/D Erase block region 2 information Number of identical-size erase block = 007Eh+1 M58LR256KC/D Erase block region 2 information Number of identical-size erase block = 00FEh+1 Erase block region 2 information Block size in region 2 = 0200h * 256 bytes
BOTTOM DEVICES
031h 032h
033h 034h 035h 038h
Reserved Reserved for future erase block region information
82/108
M58LRxxxKC, M58LRxxxKD Table 46.
Offset (P)h = 10Ah
Common Flash interface
Primary algorithm-specific extended query table
Data 0050h 0052h 0049h Primary algorithm extended query table unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Extended query table contents for primary algorithm. Address (P+5)h contains less significant byte. bit 0 Chip Erase supported(1 = Yes, 0 = No) bit 1 Erase Suspend supported(1 = Yes, 0 = No) bit 2 Program Suspend supported(1 = Yes, 0 = No) bit 3 Legacy Lock/Unlock supported(1 = Yes, 0 = No) bit 4 Queued Erase supported(1 = Yes, 0 = No) bit 5 Instant individual block locking supported(1 = Yes, 0 = No) bit 6 Protection bits supported(1 = Yes, 0 = No) bit 7 Page mode read supported(1 = Yes, 0 = No) bit 8 Synchronous read supported(1 = Yes, 0 = No) bit 9 Simultaneous operation supported(1 = Yes, 0 = No) bit 10 to 31 Reserved; undefined bits are `0'. If bit 31 is '1' then another 31 bit field of optional features follows at the end of the bit-30 field. Supported Functions after Suspend Read Array, Read Status Register and CFI Query Description Value "P" "R" "I" "1" "3"
(P+3)h =10Dh (P+4)h = 10Eh (P+5)h = 10Fh
0031h 0033h 00E6h 0003h
(P+7)h = 111h
0000h
(P+8)h = 112h
0000h
No Yes Yes No No Yes Yes Yes Yes Yes
(P+9)h = 113h
0001h bit 0 Program supported after Erase Suspend (1 = Yes, 0 = No) bit 7 to 1 Reserved; undefined bits are `0' Yes
(P+A)h = 114h
0003h
Block Protect Status Defines which bits in the Block Status Register section of the query are implemented. bit 0 Block protect Status Register Lock/Unlock bit active (1 = Yes, 0 = No) bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No) bit 15 to 2 Reserved for future use; undefined bits are `0' VDD logic supply optimum program/erase voltage (highest performance)
(P+B)h = 115h
0000h
Yes Yes
(P+C)h = 116h
0018h bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV VPP Supply Optimum Program/Erase voltage
1.8V
(P+D)h = 117h
0090h
bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV
9V
83/108
Common Flash interface Table 47.
Offset
(1)
M58LRxxxKC, M58LRxxxKD
Protection Register information
Data 0002h Description Number of protection register fields in JEDEC ID space. 0000h indicates that 256 fields are available. Value 2 80h 00h 8 bytes 8 bytes 89h Protection Register 2: Protection Description Bits 0-31 protection register address Bits 32-39 n number of factory programmed regions (lower byte) Bits 40-47 n number of factory programmed regions (upper byte) Bits 48-55 2n bytes in factory programmable region Bits 56-63 n number of user programmable regions (lower byte) Bits 64-71 n number of user programmable regions (upper byte) Bits 72-79 2n bytes in user programmable region 00h 00h 00h 0 0 0 16 0 16
(P+E)h = 118h (P+F)h = 119h (P+10)h = 11Ah (P+ 11)h = 11Bh (P+12)h = 11Ch (P+13)h = 11Dh (P+14)h = 11Eh (P+15)h = 11Fh (P+16)h = 120h (P+17)h = 121h (P+18)h = 122h (P+19)h = 123h (P+1A)h = 124h (P+1B)h = 125h (P+1C)h = 126h
0080h Protection Field 1: Protection Description 0000h Bits 0-7 Lower byte of protection register address Bits 8-15 Upper byte of protection register address 0003h Bits 16-23 2n bytes in factory pre-programmed region 0003h Bits 24-31 2n bytes in user programmable region 0089h 0000h 0000h 0000h 0000h 0000h 0000h 0010h 0000h 0004h
1. The variable P is a pointer that is defined at CFI offset 015h.
Table 48.
Offset(1)
Burst read information
Data Description Value 8 bytes
(P+1D)h = 127h
Page-mode read capability bits 0-7 n' such that 2n HEX value represents the number of 0003h read-page bytes. See offset 0028h for device word width to determine page-mode data output width. 0004h Number of synchronous mode read configuration fields that follow.
(P+1E)h = 128h
4
(P+1F)h = 129h
Synchronous mode read capability configuration 1 bit 3-7 Reserved bit 0-2 n' such that 2n+1 HEX value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. A value of 07h indicates 0001h that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the device's burstable address space. This field's 3-bit value can be written directly to the read configuration register bit 0-2 if the device is configured for its maximum word width. See offset 0028h for word width to determine the burst data output width. 0002h Synchronous mode read capability configuration 2 0003h Synchronous mode read capability configuration 3 0007h Synchronous mode read capability configuration 4
4
(P+20)h = 12Ah (P-21)h = 12Bh (P+22)h = 12Ch
8 16 Cont.
1. The variable P is a pointer that is defined at CFI offset 015h.
84/108
M58LRxxxKC, M58LRxxxKD Table 49. Bank and erase block region information(1) (2)
Flash memory (bottom)
Common Flash interface
Flash memory (top) Offset (P+23)h = 12Dh Data 02h
Description Offset (P+23)h = 12Dh Data 02h Number of bank regions within the device
1. The variable P is a pointer that is defined at CFI offset 015h. 2. bank regions. There are two bank regions, see Table 31, Table 34, Table 37 and Table 40.
Table 50.
Bank and erase block region 1 information
Flash memory (bottom) Offset(1) (P+24)h = 12Eh (P+25)h = 12Fh Description Data 01h Number of identical banks within bank region 1 00h Number of program or erase operations allowed in bank region 1: Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Number of program or erase operations allowed in other banks while a bank in same region is programming Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Number of program or erase operations allowed in other banks while a bank in this region is erasing Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Types of erase block regions in bank region 1 n = number of erase block regions with contiguous same-size erase blocks. Symmetrically blocked banks have one blocking region(2) Bank region 1 erase block type 1 information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: nx256 = number of bytes in erase block region Bank region 1 (erase block type 1) Minimum block erase cycles x 1000
Flash memory (top) Offset(1) (P+24)h = 12Eh (P+25)h = 12Fh Data 0Fh 00h
(P+26)h = 130h
11h
(P+26)h = 130h
11h
(P+27)h = 131h
00h
(P+27)h = 131h
00h
(P+28)h = 132h
00h
(P+28)h = 132h
00h
(P+29)h = 133h
01h
(P+29)h = 133h
02h
(P+2A)h = 134h (P+2B)h = 135h (P+2C)h = 136h (P+2D)h = 137h (P+2E)h = 138h (P+2F)h = 139h
07h(3) (P+2A)h = 134h 0Fh(4) 00h 00h 02h 64h 00h (P+2B)h = 135h (P+2C)h = 136h (P+2D)h = 137h (P+2E)h = 138h (P+2F)h = 139h
03h 00h 80h 00h 64h 00h
85/108
Common Flash interface Table 50.
M58LRxxxKC, M58LRxxxKD
Bank and erase block region 1 information (continued)
Flash memory (bottom) Offset(1) Description Data Bank region 1 (erase block type 1): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for "internal ECC used" BIts 5-7: reserved Bank region 1 (erase block type 1): Page mode and Synchronous mode capabilities Bit 0: Page-mode reads permitted(5) Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved
Flash memory (top) Offset(1) Data
(P+30)h = 13Ah
01h
(P+30)h = 13Ah
01h
(P+31)h = 13Bh
03h
(P+31)h = 13Bh
03h
06h(3) Bank region 1 erase block type 2 information 0Eh(4) Bits 0-15: n+1 = number of identical-sized (P+33)h = 13Dh 00h erase blocks (P+34)h = 13Eh 00h Bits 16-31: nx256 = number of bytes in erase block region (P+35)h = 13Fh 02h (P+32)h = 13Ch (P+36)h = 140h (P+37)h = 141h 64h 00h Bank region 1 (erase block type 2) Minimum block erase cycles x 1000 Bank regions 1 (erase block type 2): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for "internal ECC used" BIts 5-7: reserved Bank region 1 (erase block type 2): Page mode and Synchronous mode capabilities Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved
(P+38)h = 142h
01h
(P+39)h = 143h
03h
1. The variable P is a pointer that is defined at CFI offset 015h. 2. Bank regions. There are two bank regions, see Table 31, Table 34, Table 37 and Table 40. 3. Applies to M58LR128KC/D only. 4. Applies to M58LR256KC/D only. 5. Although the device supports Page Read mode, this is not described in the datasheet as its use is not advantageous in a multiplexed device.
86/108
M58LRxxxKC, M58LRxxxKD Table 51. Bank and erase block region 2 information
Flash memory (bottom) Offset(1) (P+3A)h = 144h (P+3B)h = 145h
Common Flash interface
Flash memory (top) Offset(1) (P+32)h = 13Ch (P+33)h = 13Dh Data 01h 00h
Description Data 0Fh Number of identical banks within bank region 2 00h Number of program or erase operations allowed in bank region 2: Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Number of program or erase operations allowed in other banks while a bank in this region is programming Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Number of program or erase operations allowed in other banks while a bank in this region is erasing Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Types of erase block regions in bank region 2 n = number of erase block regions with contiguous same-size erase blocks. Symmetrically blocked banks have one blocking region.(2)
(P+34)h = 13Eh
11h
(P+3C)h = 146h
11h
(P+35)h = 13Fh
00h
(P+3D)h = 147h
00h
(P+36)h = 140h
00h
(P+3E)h = 148h
00h
(P+37)h = 141h
02h
(P+3F)h = 149h
01h
(P+38)h = 142h (P+39)h = 143h (P+3A)h = 144h (P+3B)h = 145h (P+3C)h = 146h (P+3D)h = 147h
06h(3) (P+40)h = 14Ah 0Eh(4) 00h 00h 02h 64h 00h (P+41)h = 14Bh (P+42)h = 14Ch (P+43)h = 14Dh (P+44)h = 14Eh (P+45)h = 14Fh
07h(3) Bank region 2 erase block type 1 information 0Fh(4) Bits 0-15: n+1 = number of identical-sized 00h erase blocks 00h Bits 16-31: nx256 = number of bytes in erase block region 02h 64h 00h Bank region 2 (erase block type 1) Minimum block erase cycles x 1000 Bank region 2 (erase block type 1): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for "internal ECC used" BIts 5-7: reserved
(P+3E)h = 148h
01h
(P+46)h = 150h
01h
87/108
Common Flash interface Table 51.
M58LRxxxKC, M58LRxxxKD
Bank and erase block region 2 information (continued)
Flash memory (bottom) Offset(1) Description Data Bank region 2 (erase block type 1):Page mode and Synchronous mode capabilities (defined in Table 48) Bit 0: Page-mode reads permitted(5) Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved Bank region 2 erase block type0 2 information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: nx256 = number of bytes in erase block region Bank region 2 (erase block type 2) Minimum block erase cycles x 1000 Bank region 2 (erase block type 2): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for "internal ECC used" BIts 5-7: reserved Bank region 2 (Erase block type 2): Page mode and Synchronous mode capabilities (defined in Table 48) Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved (P+48)h = 152h (P+43)h = 153h Feature Space definitions Reserved
Flash memory (top) Offset(1) Data
(P+3F)h = 149h
03h
(P+47)h = 151h
03h
(P+40)h = 14Ah (P+41)h = 14Bh (P+42)h = 14Ch (P+43)h = 14Dh (P+44)h = 14Eh (P+45)h = 14Fh
03h 00h 80h 00h 64h 00h
(P+46)h = 150h
01h
(P+47)h = 151h
03h
(P+48)h = 152h (P+49)h = 153h
1. The variable P is a pointer which is defined at CFI offset 015h. 2. Bank regions. There are two bank regions, see Table 31, Table 34, Table 37 and Table 40. 3. Applies to M58LR128KC/D only. 4. Applies to M58LR256KC/D only. 5. Although the device supports Page Read mode, this is not described in the datasheet as its use is not advantageous in a multiplexed device.
88/108
M58LRxxxKC, M58LRxxxKD
Flowcharts and pseudocodes
Appendix C
Flowcharts and pseudocodes
Figure 17. Program flowchart and pseudocode
Start program_command (addressToProgram, dataToProgram) {: Write 40h or 10h (3) writeToFlash (addressToProgram, 0x40); /*writeToFlash (addressToProgram, 0x10);*/ /*see note (3)*/ writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/ do { status_register=readFlash (addressToProgram); "see note (3)"; /* E or G must be toggled*/ NO } while (status_register.SR7== 0) ; YES SR3 = 0 YES SR4 = 0 YES SR1 = 0 YES End } NO Program to Protected Block Error (1, 2) if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ; NO Program Error (1, 2) if (status_register.SR4==1) /*program error */ error_handler ( ) ; NO VPP Invalid Error (1, 2) if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ;
Write Address & Data
Read Status Register (3)
SR7 = 1
AI06170b
1. Status check of SR1 (protected block), SR3 (VPP Invalid) and SR4 (program error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 3. Any address within the bank can equally be used.
89/108
Flowcharts and pseudocodes Figure 18. Blank check flowchart and pseudocode
Start
M58LRxxxKC, M58LRxxxKD
blank_check_command (blockToCheck) { Write Block Address & BCh writeToFlash (blockToCheck, 0xBC);
Write Block Address & CBh
writeToFlash (blockToCheck, 0xCB); /* Memory enters read status state after the Blank Check Command */
do { Read Status Register (1) status_register = readFlash (blockToCheck); /* see note (1) */ /* E or G must be toggled */ } while (status_register.SR7==0); SR7 = 1 YES SR4 = 1 SR5 = 1 YES Command Sequence Error (2) if (status_register.SR4==1) && (status_register.SR5==1) /* command sequence error */ error_handler () ; NO
SR5 = 0
NO
Blank Check Error (2)
if (status_register.SR5==1) /* Blank Check error */ error_handler () ;
End
}
ai10520c
1. Any address within the bank can equally be used. 2. If an error is found, the Status Register must be cleared before further program/erase operations.
90/108
M58LRxxxKC, M58LRxxxKD Figure 19. Buffer program flowchart and pseudocode
Start
Flowcharts and pseudocodes
Buffer Program E8h Command, Start Address Read Status Register
Buffer_Program_command (Start_Address, n, buffer_Program[] ) /* buffer_Program [] is an array structure used to store the address and data to be programmed to the Flash memory (the address must be within the segment Start Address and Start Address+n) */ { do {writeToFlash (Start_Address, 0xE8) ;
status_register=readFlash (Start_Address);
SR7 = 1 YES Write n(1), Start Address
NO
} while (status_register.SR7==0);
writeToFlash (Start_Address, n);
Write Buffer Data, Start Address
writeToFlash (buffer_Program[0].address, buffer_Program[0].data); /*buffer_Program[0].address is the start address*/
X=0
x = 0;
X=n NO
YES
while (xWrite Next Buffer Data, Next Program Address(2)
{ writeToFlash (buffer_Program[x+1].address, buffer_Program[x+1].data);
x++; X=X+1 } Program Buffer to Flash Confirm D0h
writeToFlash (Start_Address, 0xD0);
Read Status Register
do {status_register=readFlash (Start_Address);
SR7 = 1 YES Full Status Register Check(3)
NO
} while (status_register.SR7==0);
full_status_register_check(); }
End
AI08913b
1. n + 1 is the number of data being programmed. 2. Next program data is an element belonging to buffer_Program[].data; next program address is an element belonging to buffer_Program[].address 3. Routine for error check by reading SR3, SR4 and SR1.
91/108
Flowcharts and pseudocodes
M58LRxxxKC, M58LRxxxKD
Figure 20. Program suspend and resume flowchart and pseudocode
Start program_suspend_command ( ) { writeToFlash (any_address, 0xB0) ; writeToFlash (bank_address, 0x70) ; /* read status register to check if program has already completed */ Write 70h do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/
Write B0h
Read Status Register
SR7 = 1 YES SR2 = 1
NO
} while (status_register.SR7== 0) ;
NO
Program Complete
if (status_register.SR2==0) /*program completed */ { writeToFlash (bank_address, 0xFF) ; read_data ( ) ; /*The device returns to Read Array (as if program/erase suspend was not issued).*/ } else { writeToFlash (bank_address, 0xFF) ;
Write FFh
YES Write FFh
Read Data
Read data from another address
read_data ( ); /*read data from another address*/
Write D0h
writeToFlash (any_address, 0xD0) ; /*write 0xD0 to resume program*/
Write 70h(1) } Program Continues with Bank in Read Status Register Mode }
writeToFlash (bank_address, 0x70) ; /*read status register to check if program has completed */
AI10117b
1. The Read Status Register command (Write 70h) can be issued just before or just after the Program Resume command.
92/108
M58LRxxxKC, M58LRxxxKD Figure 21. Block erase flowchart and pseudocode
Flowcharts and pseudocodes
Start erase_command ( blockToErase ) { writeToFlash (blockToErase, 0x20) ; /*see note (2) */ writeToFlash (blockToErase, 0xD0) ; /* Memory enters read status state after the Erase Command */
Write 20h (2)
Write Block Address & D0h
Read Status Register (2)
do { status_register=readFlash (blockToErase) ; /* see note (2) */ /* E or G must be toggled*/
SR7 = 1
NO } while (status_register.SR7== 0) ;
YES SR3 = 0 YES SR4, SR5 = 1 NO SR5 = 0 YES SR1 = 0 YES End } NO Erase to Protected Block Error (1) if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ; NO Erase Error (1) if ( (status_register.SR5==1) ) /* erase error */ error_handler ( ) ; YES Command Sequence Error (1) if ( (status_register.SR4==1) && (status_register.SR5==1) ) /* command sequence error */ error_handler ( ) ; NO VPP Invalid Error (1) if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ;
AI10976
1. If an error is found, the Status Register must be cleared before further program/erase operations. 2. Any address within the bank can equally be used.
93/108
Flowcharts and pseudocodes Figure 22. Erase suspend and resume flowchart and pseudocode
Start
M58LRxxxKC, M58LRxxxKD
Write B0h
erase_suspend_command ( ) { writeToFlash (bank_address, 0xB0) ; writeToFlash (bank_address, 0x70) ; /* read status register to check if erase has already completed */
Write 70h
Read Status Register
do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/
SR7 = 1 YES SR6 = 1
NO
} while (status_register.SR7== 0) ;
NO
Erase Complete
if (status_register.SR6==0) /*erase completed */ { writeToFlash (bank_address, 0xFF) ;
Write FFh
Read Data YES Write FFh else }
read_data ( ) ; /*The device returns to Read Array (as if program/erase suspend was not issued).*/
{ writeToFlash (bank_address, 0xFF) ; read_program_data ( ); /*read or program data from another block*/
Read data from another block or Program or Block Lock/Unlock/Lock-Down or Set Configuration Register
writeToFlash (bank_address, 0xD0) ; /*write 0xD0 to resume erase*/ writeToFlash (bank_address, 0x70) ; /*read status register to check if erase has completed */ } }
Write D0h
Write 70h(1)
Erase Continues with Bank in Read Status Register Mode
AI10116c
1. The Read Status Register command (Write 70h) can be issued just before or just after the Erase Resume command.
94/108
M58LRxxxKC, M58LRxxxKD Figure 23. Locking operations flowchart and pseudocode
Flowcharts and pseudocodes
Start
Write 60h (1)
locking_operation_command (address, lock_operation) { writeToFlash (address, 0x60) ; /*configuration setup*/ /* see note (1) */ if (lock_operation==LOCK) /*to protect the block*/ writeToFlash (address, 0x01) ; else if (lock_operation==UNLOCK) /*to unprotect the block*/ writeToFlash (address, 0xD0) ; else if (lock_operation==LOCK-DOWN) /*to lock the block*/ writeToFlash (address, 0x2F) ; writeToFlash (address, 0x90) ; /*see note (1) */
Write 01h, D0h or 2Fh
Write 90h (1)
Read Block Lock States
Locking change confirmed? YES Write FFh (1)
NO
if (readFlash (address) ! = locking_state_expected) error_handler () ; /*Check the locking state (see Read Block Signature table )*/
writeToFlash (address, 0xFF) ; /*Reset to Read Array mode*/ /*see note (1) */ }
End
AI06176b
1. Any address within the bank can equally be used.
95/108
Flowcharts and pseudocodes Figure 24. Protection Register program flowchart and pseudocode
M58LRxxxKC, M58LRxxxKD
Start
Write C0h (3)
protection_register_program_command (addressToProgram, dataToProgram) {: writeToFlash (addressToProgram, 0xC0) ; /*see note (3) */ writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/ do { status_register=readFlash (addressToProgram) ; /* see note (3) */ /* E or G must be toggled*/ NO } while (status_register.SR7== 0) ;
Write Address & Data
Read Status Register (3)
SR7 = 1 YES SR3 = 0 YES SR4 = 0 YES SR1 = 0 YES End
NO
VPP Invalid Error (1, 2)
if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ;
NO
Program Error (1, 2)
if (status_register.SR4==1) /*program error */ error_handler ( ) ;
NO
Program to Protected Block Error (1, 2)
if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ;
}
AI06177b
1. Status check of SR1 (protected block), SR3 (VPP invalid) and SR4 (program error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 3. Any address within the bank can equally be used.
96/108
M58LRxxxKC, M58LRxxxKD
Flowcharts and pseudocodes
Figure 25. Buffer enhanced factory program flowchart and pseudocode
Start Write 80h to Address WA1 SETUP PHASE
Buffer_Enhanced_Factory_Program_Command (start_address, DataFlow[]) {
writeToFlash (start_address, 0x80) ;
Write D0h to Address WA1
writeToFlash (start_address, 0xD0) ; do { do { status_register = readFlash (start_address);
Read Status Register
NO
SR7 = 0 YES
NO
SR4 = 1
Initialize count X=0 Write PDX Address WA1
if (status_register.SR4==1) { /*error*/ if (status_register.SR3==1) error_handler ( ) ;/*VPP error */ if (status_register.SR1==1) error_handler ( ) ;/* Locked Block */ PROGRAM AND } VERIFY PHASE while (status_register.SR7==1) x=0; /* initialize count */ do { writeToFlash (start_address, DataFlow[x]);
Read Status Register SR3 and SR1for errors
Exit
Increment Count X=X+1
x++;
NO
X = 32 YES Read Status Register
}while (x<32) do {
status_register = readFlash (start_address);
NO
SR0 = 0 YES
}while (status_register.SR0==1)
NO
Last data? YES Write FFFFh to Address = NOT WA1
} while (not last data)
writeToFlash (another_block_address, FFFFh)
EXIT PHASE
Read Status Register
do { status_register = readFlash (start_address)
NO
SR7 = 1
}while (status_register.SR7==0)
YES Full Status Register Check End
full_status_register_check();
}
AI07302a
97/108
Command interface state tables
M58LRxxxKC, M58LRxxxKD
Appendix D
Table 52.
Command interface state tables
Command interface states - modify table, next state(1)
Command Input Erase Read Confirm Buffer Clear Electronic Blank P/E Resume, Blank Program, Read Status Check Block Unlock Check Program/ Status Register Signature , Read confirm, confirm Erase Register setup (5) CFI Query BEFP (CBh) Suspend (70h) (BCh) (3)(4) (50h) Confirm (B0h) (90h, 98h) (D0h) Blank Check setup Ready (unlock block) OTP Busy OTP Busy IS in OTP Busy OTP busy IS in OTP Busy OTP Busy
Current CI State
Block Buffer BEFP Read Program Program Erase, (3)(4) Setup Array(2) Setup (3)(4) Setup(3)(4) (FFh) (80h) (10/40h) (E8h) (20h)
Ready
Ready
Program Setup
BP Setup
Erase Setup
BEFP Setup
Ready
Lock/CR Setup Setup Busy OTP IS in OTP busy Setup
Ready (Lock Error)
Ready (Lock Error)
OTP Busy
Program Busy IS in Program Program Program Busy Busy Busy IS in Program Busy Program Suspend
Busy
Program Busy
Program Busy
Program
IS in Program Busy Suspend IS in PS Setup Buffer Load 1 Buffer Load 2 Confirm PS IS in PS PS IS in Program Suspend
Program Busy
PS
Program Busy
Program Suspend
Program Suspend Buffer Program Load 1 (give word count load (N-1)); if N=0 go to Buffer Program Confirm. Else (N 0) go to Buffer Program Load 2 (data load) Buffer Program Confirm when count =0; Else Buffer Program Load 2 (note: Buffer Program will fail at this point if any block address is different from the first address) Ready (error) BP Busy IS in BP Busy BP Busy IS in BP Busy BP Busy BP Busy Ready (error) BP Suspend Buffer Program Busy
Buffer Program
Busy IS in BP Busy Suspend IS in BP Suspend
Buffer Program Busy BP BP IS in BP BP IS in BP Suspend Suspend Suspend Suspend Suspend
BP busy
Buffer Program Suspend
Buffer Program Suspend
98/108
M58LRxxxKC, M58LRxxxKD Table 52.
Command interface state tables
Command interface states - modify table, next state(1) (continued)
Command Input Erase Read Confirm Buffer Clear Electronic Blank P/E Resume, Blank Program, Read Status Check Block Unlock Check Program/ Status Register Signature , Read confirm, setup confirm Erase Register (5) CFI Query BEFP (BCh) (CBh) Suspend (70h) (3)(4) (50h) Confirm (B0h) (90h, 98h) (D0h) Erase Busy Erase Busy Ready (error) Erase Suspend Erase Busy
Current CI State
Block Buffer BEFP Read Program Program Erase, (3)(4) Setup Array(2) Setup (3)(4) Setup(3)(4) (FFh) (80h) (10/40h) (E8h) (20h)
Setup Busy IS in Erase Busy Suspend IS in ES Setup IS in Program Program Busy in Busy in ES ES Erase Busy IS in Erase Busy
Ready (error) Erase Busy IS in Erase Busy
Erase
Erase Busy
Erase Program BP in ES Suspend in ES
IS in Erase Suspend
ES
Erase Busy
Erase Suspend
Erase Suspend Program Busy in Erase Suspend Program Busy in ES
Busy
IS in Program Busy in ES
Program Busy in ES
PS in ES
Program Busy in Erase Suspend
Program IS in in Erase Program Suspend busy in ES Suspend PS in ES IS in PS in ES Setup Buffer Load 1 IS in PS in PS in ES ES
Program busy in Erase Suspend
IS in Program Suspend in ES
PS in ES
Program Busy in ES
Program Suspend in Erase Suspend
Program Suspend in Erase Suspend Buffer Program Load 1 in Erase Suspend (give word count load (N-1)); if N=0 go to Buffer Program confirm. Else (N 0) go to Buffer Program Load 2 Buffer Program Load 2 in Erase Suspend (data load)
Buffer Buffer Program Confirm in Erase Suspend when count =0; Else Buffer Program Load 2 in Erase Suspend (note: Buffer Program Load 2 will fail at this point if any block address is different from the first address) Confirm Buffer Program in Erase Suspend BP Busy in ES Erase Suspend (sequence error) IS in BP Busy in ES BP busy in ES IS in BP busy in ES BP Busy in ES Erase Suspend (sequence error) BP Suspend in ES
Busy
BP Busy in ES
Buffer Program Busy in ES
IS in BP busy in ES
Buffer Program Busy in Erase Suspend
BP BP IS in BP BP IS in BP Suspend Suspend Suspend Suspend in Erase Suspend Suspend Suspend in ES in ES in ES in ES IS in BP Suspend in ES
BP Busy in Erase Suspend
Buffer Program Suspend in Erase Suspend
BP Suspend in Erase Suspend
99/108
Command interface state tables Table 52.
M58LRxxxKC, M58LRxxxKD
Command interface states - modify table, next state(1) (continued)
Command Input Erase Read Confirm Buffer Clear Electronic Blank P/E Resume, Blank Program, Read Status Check Block Unlock Check Program/ Status Register Signature , Read confirm, setup confirm Erase Register (5) CFI Query BEFP (BCh) (CBh) Suspend (70h) (3)(4) (50h) Confirm (B0h) (90h, 98h) (D0h) Blank Check busy Blank Check busy
Current CI State
Block Buffer BEFP Read Program Program Erase, (3)(4) Setup Array(2) Setup (3)(4) Setup(3)(4) (FFh) (80h) (10/40h) (E8h) (20h)
Setup Blank Check Busy Blank IS in Blank Check Check busy busy Blank Check busy
Ready (error)
Ready (error)
IS in Blank Check busy Erase Suspend BEFP Busy BEFP Busy(6)
Lock/CR Setup in Erase Suspend Buffer EFP Setup Busy
Erase Suspend (Lock Error) Ready (error)
Erase Suspend (Lock Error) Ready (error)
1. CI = Command Interface, CR = Configuration register, BEFP = Buffer Enhanced Factory program, P/E C = Program/Erase controller, IS = Illegal State, BP = Buffer Program, ES = Erase Suspend. 2. At power-up, all banks are in read array mode. Issuing a Read Array command to a busy bank, results in undetermined data output. 3. The two cycle command should be issued to the same bank address. 4. If the P/E C is active, both cycles are ignored. 5. The Clear Status Register command clears the SR error bits except when the P/E C. is busy or suspended. 6. BEFP is allowed only when Status Register bit SR0 is reset to '0'. BEFP is busy if Block Address is first BEFP Address. Any other commands are treated as data.
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M58LRxxxKC, M58LRxxxKD Table 53.
Command interface state tables
Command interface states - modify table, next output state(1) (2)
Command Input Erase Confirm Block Blank P/E Resume, Buffer Erase, BEFP Block Unlock (4) Setup Check Program Setup (5) setup confirm, BEFP (5) (E8h) (80h) (BCh) Confirm(4)(5) (10/40h) (20h) (D0h) Read Clear Electronic Blank Program/ Read Status Status signature, Check Erase confirm Suspend Register Register Read CFI Query (CBh) (B0h) (70h) (50h) (90h, 98h)
Current CI State
Read Program Array Setup(4)
(3)
(FFh)
Program Setup Erase Setup OTP Setup Program Setup in Erase Suspend BEFP Setup BEFP Busy Buffer Program Setup Buffer Program Load 1 Buffer Program Load 2 Buffer Program Confirm Buffer Program Setup in Erase Suspend Buffer Program Load 1 in Erase Suspend Buffer Program Load 2 in Erase Suspend Buffer Program Confirm in Erase Suspend Blank Check setup Lock/CR Setup Lock/CR Setup in Erase Suspend
Status Register
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Command interface state tables Table 53.
M58LRxxxKC, M58LRxxxKD
Command interface states - modify table, next output state(1) (2) (continued)
Command Input Erase Confirm Block Blank P/E Resume, Buffer Erase, BEFP Block Unlock (4) Setup Check Program Setup (5) setup confirm, BEFP (5) (E8h) (80h) (BCh) Confirm(4)(5) (10/40h) (20h) (D0h) Read Clear Electronic Blank Program/ Read Status Status signature, Check Erase confirm Suspend Register Register Read CFI Query (CBh) (B0h) (70h) (50h) (90h, 98h) Status Register
Current CI State
Read Program Array Setup(4)
(3)
(FFh)
OTP Busy Ready Program Busy Erase Busy Buffer Program Busy Program/Erase Suspend Buffer Program Suspend Program Busy in Erase Suspend Buffer Program Busy in Erase Suspend Program Suspend in Erase Suspend Buffer Program Suspend in Erase Suspend Blank Check busy Illegal State Output Unchanged
Array
Status Register
Output Unchanged
Output Status Unchang Electronic Register ed Signature/ CFI
1. The output state shows the type of data that appears at the outputs if the bank address is the same as the command address. A bank can be placed in Read Array, Read Status Register, Read Electronic Signature or Read CFI mode, depending on the command issued. Each bank remains in its last output state until a new command is issued to that bank. The next state does not depend on the bank output state. 2. CI = Command Interface, CR = Configuration Register, BEFP = Buffer Enhanced Factory Program, P/E. C. = Program/Erase Controller. 3. At Power-Up, all banks are in read array mode. Issuing a Read Array command to a busy bank, results in undetermined data output. 4. The two cycle command should be issued to the same bank address. 5. If the P/EC is active, both cycles are ignored.
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M58LRxxxKC, M58LRxxxKD Table 54. Command interface states - lock table, next state(1)
Command Input Block Lock Confirm (01h) Block LockDown Confirm (2Fh)
Command interface state tables
Current CI State
Lock/CR Setup(2) (60h)
OTP Setup(2) (C0h)
Set CR Confirm (03h)
Block Address (WA0)(3) (XXXXh)
Illegal Command(4)
P/E C operation completed
(5)
Ready Lock/CR Setup Setup OTP Busy IS in OTP busy Setup Busy Program IS in Program busy Suspend IS in PS Setup Buffer Load 1 Buffer Load 2 Confirm Buffer Program Busy IS in Buffer Program busy Suspend IS in BP Suspend Setup Busy IS in Erase busy Suspend IS in ES
Lock/CR Setup
OTP Setup Ready OTP Busy
Ready Ready (Lock error)
N/A N/A N/A
Ready (Lock error)
IS in OTP Busy OTP Busy Program Busy IS in Program Busy Program busy IS in PS
OTP Busy
Ready IS Ready N/A
Program Busy
Ready IS Ready
Program Suspend N/A Program Suspend Buffer Program Load 1 (give word count load (N-1)); Buffer Program Load 2(6) Exit see note (6) N/A N/A N/A N/A Buffer Program Busy Ready
Buffer Program Confirm when count =0; Else Buffer Program Load 2 (note: Buffer Program will fail at this point if any block address is different from the first address) Ready (error) IS in BP Busy
Buffer Program Busy
IS Ready
IS in BP Suspend
Buffer Program Suspend N/A Buffer Program Suspend Ready (error) N/A Erase Busy Erase Busy Ready IS ready
IS in Erase Busy
Erase
Lock/CR Setup in ES
IS in ES Erase Suspend
Erase Suspend N/A
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Command interface state tables Table 54.
M58LRxxxKC, M58LRxxxKD
Command interface states - lock table, next state(1) (continued)
Command Input Block Lock Confirm (01h) Block LockDown Confirm (2Fh) Block Address (WA0)(3) (XXXXh) P/E C operation completed
(5)
Current CI State
Lock/CR Setup(2) (60h)
OTP Setup(2) (C0h)
Set CR Confirm (03h)
Illegal Command(4)
Setup Busy Program in Erase Suspend IS in Program busy in ES Suspend IS in PS in ES Setup Buffer Load 1 IS in PS in ES IS in Program busy in ES
Program Busy in Erase Suspend Program Busy in Erase Suspend Program Busy in Erase Suspend Program Suspend in Erase Suspend
N/A ES IS in ES
N/A Program Suspend in Erase Suspend Buffer Program Load 1 in Erase Suspend (give word count load (N-1)) Buffer Program Load 2 in Erase Suspend(7) Exit see note (7) N/A
Buffer Load 2
Buffer Program Confirm in Erase Suspend when count =0; Else Buffer Program Load 2 in Erase Suspend (note: Buffer Program will fail at this point if any block address is different from the first address) Erase Suspend (sequence error) IS in BP busy in ES Buffer Program Busy in Erase Suspend BP busy in ES IS in BP suspend in ES Buffer Program Suspend in Erase Suspend
Buffer Program in Erase Suspend
Confirm Busy IS in BP busy in ES Suspend IS in BP Suspend in ES Setup
ES IS in ES
N/A Buffer Program Suspend in Erase Suspend
Ready (error) IS in Blank Check busy Erase Suspend (Lock error) Blank Check busy Erase Suspend Ready (error) BEFP Busy(8) Exit BEFP Busy(8) Erase Suspend (Lock error)
N/A Ready N/A N/A N/A
Blank Check
Blank Check busy
Lock/CR Setup in ES Setup BEFP Busy
1. CI = Command Interface, CR = Configuration register, BEFP = Buffer Enhanced Factory program, P/E C = Program/Erase controller, IS = Illegal State, BP = Buffer program, ES = Erase suspend, WA0 = Address in a block different from first BEFP address. 2. If the P/E C is active, both cycle are ignored. 3. BEFP Exit when Block Address is different from first Block Address and data are FFFFh. 4. Illegal commands are those not defined in the command set. 5. N/A: not available. In this case the state remains unchanged. 6. If N=0 go to Buffer Program Confirm. Else (not =0) go to Buffer Program Load 2 (data load) 7. If N=0 go to Buffer Program Confirm in Erase suspend. Else (not =0) go to Buffer Program Load 2 in Erase suspend. 8. BEFP is allowed only when Status Register bit SR0 is set to '0'. BEFP is busy if Block Address is first BEFP Address. Any other commands are treated as data.
104/108
M58LRxxxKC, M58LRxxxKD Table 55.
Command interface state tables
Command interface states - lock table, next output state (1) (2)
Command Input
Current CI State
Lock/CR Setup(3)( 60h)
Blank Check setup (BCh)
OTP Setup(3) (C0h)
Blank Check confirm (CBh)
P. E./C. Illegal Block Lock Block Lock- Set CR BEFP Confirm Down Confirm Exit(4) Command Operation (5) Completed (01h) Confirm (2Fh) (03h) (FFFFh)
Program Setup Erase Setup OTP Setup Program Setup in Erase Suspend BEFP Setup BEFP Busy Buffer Program Setup Buffer Program Load 1 Status Register Buffer Program Load 2 Buffer Program Confirm Buffer Program Setup in Erase Suspend Buffer Program Load 1 in Erase Suspend Buffer Program Load 2 in Erase Suspend Buffer Program Confirm in Erase Suspend Blank Check setup Lock/CR Setup Lock/CR Setup in Erase Suspend Status Register Array Status Register Output Unchanged
105/108
Command interface state tables Table 55.
M58LRxxxKC, M58LRxxxKD
Command interface states - lock table, next output state (continued)(1) (2)
Command Input
Current CI State
Lock/CR Setup(3)( 60h)
Blank Check setup (BCh)
OTP Setup(3) (C0h)
Blank Check confirm (CBh)
P. E./C. Block Lock Block Lock- Set CR BEFP Illegal Confirm Down Confirm Exit(4) Command Operation (5) Completed (01h) Confirm (2Fh) (03h) (FFFFh)
OTP Busy Ready Program Busy Erase Busy Buffer Program Busy Program/Erase Suspend Buffer Program Suspend Status Register Program Busy in Erase Suspend Buffer Program Busy in Erase Suspend Program Suspend in Erase Suspend Buffer Program Suspend in Erase Suspend Blank Check busy Illegal State Output Unchanged Output Unchanged Array Output Unchanged
1. The output state shows the type of data that appears at the outputs if the bank address is the same as the command address. A bank can be placed in Read Array, Read Status Register, Read Electronic Signature or Read CFI mode, depending on the command issued. Each bank remains in its last output state until a new command is issued to that bank. The next state does not depend on the bank's output state. 2. CI = Command Interface, CR = Configuration Register, BEFP = Buffer Enhanced Factory Program, P/E. C. = Program/Erase Controller. 3. If the P/EC is active, both cycles are ignored. 4. BEFP Exit when Block Address is different from first Block Address and data are FFFFh. 5. Illegal commands are those not defined in the command set.
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M58LRxxxKC, M58LRxxxKD
Revision history
14
Table 56.
Date
Revision history
Document revision history
Revision 1 2 3 Initial release. Added 256 Mb density device to document to make the M58LRxxxKCD family datasheet. Applied Numonyx branding. Changes
09-Jul-2007 28-Feb-2008 20-Mar-2008
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M58LRxxxKC, M58LRxxxKD
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